公开(公告)号：WO2012000821A1

公开(公告)日：2012-01-05

申请号：PCT/EP2011/060251

申请日：2011-06-20

Applicant: S.O.I.TEC SILICON ON INSULATOR TECHNOLOGIES ,  DELPRAT, Daniel ,  DURET, Carine ,  BEN MOHAMED, Nadia ,  LALLEMENT, Fabrice

Inventor： DELPRAT, Daniel ,  DURET, Carine ,  BEN MOHAMED, Nadia ,  LALLEMENT, Fabrice

IPC: H01L21/762

CPC classification number: H01L21/76254

Abstract: The present invention concerns a method for reducing irregularities at the surface of a layer (4) transferred from a source substrate (1) to a glass-based support substrate (3), wherein said transfer comprises the steps of: (a) generating a weakening zone (2) in the source substrate (1); (b) contacting the source substrate (1) and the glass-based support substrate (3); (c) splitting the source substrate (1) at the weakening zone (2); characterized in that the thickness of the glass-based substrate is comprised between 300 μm and 600 μm.

Abstract translation: 本发明涉及一种减少从源极基板（1）转移到玻璃基支撑基板（3）的层（4）的表面上的不规则性的方法，其中所述转移包括以下步骤：（a）产生 源基片（1）中的弱化区（2）; （b）使所述源极衬底（1）和所述玻璃基支撑衬底（3）接触; （c）在弱化区（2）处分离源极衬底（1）; 其特征在于，所述玻璃基板的厚度为300μm〜600μm。

公开(公告)号：WO2011123199A1

公开(公告)日：2011-10-06

申请号：PCT/US2011/025647

申请日：2011-02-22

Applicant: S.O.I.TEC SILICON ON INSULATOR TECHNOLOGIES ,  MAZURE, Carlos ,  NGUYEN, Bich-Yen ,  SADAKA, Mariam

Inventor： MAZURE, Carlos ,  NGUYEN, Bich-Yen ,  SADAKA, Mariam

IPC: H01L27/06 ,  H01L21/822

CPC classification number: H01L27/0688 ,  H01L21/02532 ,  H01L21/0262 ,  H01L21/02667 ,  H01L21/187 ,  H01L21/8221 ,  H01L2924/00011 ,  H01L2224/80001

Abstract: Methods of forming semiconductor structures include transferring a portion (116a) of a donor structure to a processed semiconductor structure (102) that includes at least one non-planar surface. An amorphous film (144) may be formed over at least one non-planar surface of the bonded semiconductor structure, and the amorphous film may be planarized to form one or more planarized surfaces. Semiconductor structures include a bonded semiconductor structure having at least one non-planar surface, and an amorphous film disposed over the at least one non-planar surface. The bonded semiconductor structure may include a processed semiconductor structure and a portion of a single crystal donor structure attached to a non-planar surface of the processed semiconductor structure.

Abstract translation: 形成半导体结构的方法包括将施主结构的部分（116a）转移到包括至少一个非平面表面的经处理的半导体结构（102）。 可以在结合的半导体结构的至少一个非平面表面上形成非晶膜（144），并且非晶膜可以被平坦化以形成一个或多个平坦化表面。 半导体结构包括具有至少一个非平面表面的键合半导体结构和设置在所述至少一个非平面表面上的非晶膜。 键合的半导体结构可以包括处理的半导体结构和附接到处理的半导体结构的非平面表面的单晶体施主结构的一部分。

公开(公告)号：WO2011097102A1

公开(公告)日：2011-08-11

申请号：PCT/US2011/022622

申请日：2011-01-26

Applicant: S.O.I.TEC SILICON ON INSULATOR TECHNOLOGIES ,  SADAKA, Marian ,  IONUT, Radu

Inventor： SADAKA, Marian ,  IONUT, Radu

IPC: H01L21/98 ,  H01L21/3105 ,  H01L21/60 ,  H01L23/00

CPC classification number: H01L24/02 ,  H01L21/3105 ,  H01L21/31053 ,  H01L24/03 ,  H01L24/05 ,  H01L24/80 ,  H01L25/50 ,  H01L2224/0401 ,  H01L2224/80896 ,  H01L2224/81894 ,  H01L2224/83894 ,  H01L2224/83896 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01014 ,  H01L2924/01015 ,  H01L2924/01022 ,  H01L2924/01023 ,  H01L2924/01027 ,  H01L2924/01028 ,  H01L2924/01029 ,  H01L2924/0103 ,  H01L2924/01032 ,  H01L2924/01033 ,  H01L2924/01044 ,  H01L2924/01049 ,  H01L2924/01051 ,  H01L2924/01073 ,  H01L2924/01074 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/04941 ,  H01L2924/04953 ,  H01L2924/05042 ,  H01L2924/12041 ,  H01L2924/12042 ,  H01L2924/1306 ,  H01L2924/14 ,  H01L2924/1461 ,  H01L2924/00

Abstract: Embodiments of the invention include methods and structures for fabricating a semiconductor structure, and, particularly for improving the planarity of a bonded semiconductor structure comprising a processed semiconductor structure and a semiconductor structure.

Abstract translation: 本发明的实施例包括用于制造半导体结构的方法和结构，特别是用于改善包括处理的半导体结构和半导体结构的键合半导体结构的平面性。

公开(公告)号：WO2011097042A1

公开(公告)日：2011-08-11

申请号：PCT/US2011/020100

申请日：2011-01-04

Applicant: S.O.I.TEC SILICON ON INSULATOR TECHNOLOGIES ,  SADAKA, Mariam ,  IONUT, Radu

Inventor： SADAKA, Mariam ,  IONUT, Radu

IPC: H01L21/98 ,  H01L21/60 ,  H01L23/00 ,  H01L21/3105

CPC classification number: H01L25/50 ,  H01L21/31053 ,  H01L23/3178 ,  H01L24/05 ,  H01L24/80 ,  H01L25/0657 ,  H01L2224/0391 ,  H01L2224/05571 ,  H01L2224/05624 ,  H01L2224/05647 ,  H01L2224/05657 ,  H01L2224/05676 ,  H01L2224/05681 ,  H01L2224/05686 ,  H01L2224/08146 ,  H01L2224/80894 ,  H01L2224/83894 ,  H01L2225/06513 ,  H01L2225/06541 ,  H01L2924/00014 ,  H01L2924/0002 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01014 ,  H01L2924/01015 ,  H01L2924/01022 ,  H01L2924/01023 ,  H01L2924/01024 ,  H01L2924/01027 ,  H01L2924/01028 ,  H01L2924/01029 ,  H01L2924/0103 ,  H01L2924/01032 ,  H01L2924/01033 ,  H01L2924/01044 ,  H01L2924/01049 ,  H01L2924/01051 ,  H01L2924/01057 ,  H01L2924/01072 ,  H01L2924/01073 ,  H01L2924/01074 ,  H01L2924/014 ,  H01L2924/04941 ,  H01L2924/04953 ,  H01L2924/05042 ,  H01L2924/12042 ,  H01L2924/14 ,  H01L2924/00012 ,  H01L2224/05552 ,  H01L2924/00

Abstract: The invention provides methods and structures for fabricating a semiconductor structure and particularly for forming a semiconductor structure with improved planarity for achieving a bonded semiconductor structure comprising a processed semiconductor structure and a number of bonded semiconductor layers. Methods for forming semiconductor structures include forming a dielectric layer over a non planar surface of a processed semiconductor structure, planarizing a surface of the dielectric layer on a side thereof opposite the processed semiconductor structure, and attaching a semiconductor structure to the planarized surface of the dielectric layer. Semiconductor structures include a dielectric layer overlaying a non planar surface of a processed semiconductor structure, and a masking layer overlaying the dielectric layer on a side thereof opposite the processed semiconductor structure. The masking layer includes a plurality of mask openings over conductive regions of the non planar surface of the processed semiconductor structure.

Abstract translation: 本发明提供了用于制造半导体结构的方法和结构，特别是用于形成具有改善的平坦度的半导体结构，以实现包括经处理的半导体结构和多个键合半导体层的键合半导体结构。 用于形成半导体结构的方法包括在经处理的半导体结构的非平坦表面上形成电介质层，在介电层的与处理的半导体结构相对的一侧上的表面平坦化，以及将半导体结构附着到电介质的平坦化表面 层。 半导体结构包括覆盖处理的半导体结构的非平面表面的介电层和覆盖在与处理的半导体结构相对的一侧上的电介质层的掩模层。 掩模层包括处理的半导体结构的非平面表面的导电区域上的多个掩模开口。

公开(公告)号：WO2010112540A1

公开(公告)日：2010-10-07

申请号：PCT/EP2010/054276

申请日：2010-03-31

Applicant: S.O.I.TEC SILICON ON INSULATOR TECHNOLOGIES ,  COMMISSARIAT A L'ENERGIE ATOMIQUE ET AUX ENERGIES ALTERNATIVES ,  ARENA, Chantal ,  CLAVELIER, Laurent ,  RABAROT, Marc

Inventor： ARENA, Chantal ,  CLAVELIER, Laurent ,  RABAROT, Marc

IPC: H01L21/20 ,  H01L21/02

CPC classification number: H01L21/02639 ,  H01L21/0237 ,  H01L21/0242 ,  H01L21/02458 ,  H01L21/0254

Abstract: The invention provides methods and structures for reducing surface dislocations of a semiconductor layer, and can be employed during the epitaxial growth of semiconductor structures and layers comprising Ill-nitride materials. Embodiments involve the formation of a plurality of dislocation pit plugs to prevent propagation of dislocations from an underlying layer of material into a following semiconductor layer of material.

Abstract translation: 本发明提供了用于减少半导体层表面位错的方法和结构，并且可以在半导体结构和包含III族氮化物材料的层的外延生长期间使用。 实施例涉及形成多个位错坑塞，以防止位错从材料的下层扩散到随后的材料半导体层中。

公开(公告)号：WO2010106101A1

公开(公告)日：2010-09-23

申请号：PCT/EP2010/053460

申请日：2010-03-17

Applicant: S.O.I.TEC SILICON ON INSULATOR TECHNOLOGIES ,  SCHWARZENBACH, Walter ,  KERDILES, Sébastien ,  REYNAUD, Patrick ,  ECARNOT, Ludovic ,  NEYRET, Eric

Inventor： SCHWARZENBACH, Walter ,  KERDILES, Sébastien ,  REYNAUD, Patrick ,  ECARNOT, Ludovic ,  NEYRET, Eric

IPC: H01L21/762

CPC classification number: H01L21/76254 ,  H01L21/02238 ,  H01L21/02255 ,  H01L21/02312 ,  H01L21/30604 ,  H01L21/31662

Abstract: The invention concerns a finishing method for a substrate (1) of silicon-on-insulator SOI type, comprising an oxide layer (3) buried between an active silicon layer (4) and a support layer(2) in silicon, this method comprising the application of finishing steps whose successive steps are:a)rapid thermal annealing RTA of said substrate (1) b)sacrificial oxidation step of its active layer (4), c)rapid thermal annealing RTA of said substrate obtained after step (b), d)sacrificial oxidation step of said active layer of the substrate (1') which underwent step c), this method being characterized in that sacrificial oxidation step b) is conducted so as to remove a first oxide thickness (5) and in that sacrificial oxidation step d) is conducted so as to remove a second oxide thickness thinner than the first.

Abstract translation: 本发明涉及一种用于绝缘体上硅SOI类型的衬底（1）的精加工方法，其包括掩埋在硅中的活性硅层（4）和支撑层（2）之间的氧化物层（3），该方法包括 应用后续步骤为：a）所述衬底（1）的快速热退火RTA b）其活性层（4）的牺牲氧化步骤，c）在步骤（b）之后获得的所述衬底的快速热退火RTA， ，d）经历步骤c）的所述基板（1'）的有源层的牺牲氧化步骤，其特征在于，进行牺牲氧化步骤b）以除去第一氧化物厚度（5），并且因此 进行牺牲氧化步骤d）以除去比第一氧化物薄的第二氧化物厚度。

公开(公告)号：WO2010103356A1

公开(公告)日：2010-09-16

申请号：PCT/IB2010/000296

申请日：2010-02-15

Applicant: S.O.I.TEC SILICON ON INSULATOR TECHNOLOGIES ,  GUÉNARD, Pascal ,  DUPONT, Frédéric

Inventor： GUÉNARD, Pascal ,  DUPONT, Frédéric

IPC: H01L21/762

CPC classification number: H01L21/76251

Abstract: The invention relates to a method of adapting the lattice parameter of a seed layer (3) of a strained material, comprising the following successive steps: a) a structure (10) is provided that has a seed layer (3) of strained material, of lattice parameter A 1 , of nominal lattice parameter A n and of thermal expansion coefficient CTE3, a low viscosity layer (2) and an intermediate substrate (1 ) of thermal expansion coefficient CTE1; b) a heat treatment is applied so as to relax the seed layer (3) of strained material; and c) the seed layer (3) is transferred onto a support substrate (5) of thermal expansion coefficient CTE5, the intermediate substrate (1 ) and the support substrate (5) being chosen so that A1 n and CTE1 CTE1 or A 1 > A n and CTE1≥ CTE3 and CTE5

Abstract translation: 本发明涉及一种适应应变材料的种子层（3）的晶格参数的方法，包括以下连续步骤：a）提供具有应变材料种子层（3）的结构（10） 的晶格参数A1，热膨胀系数CTE3的热膨胀系数CTE3，低粘度层（2）和热膨胀系数CTE1的中间基板（1）的晶格参数A1， b）施加热处理以松弛应变材料的种子层（3）; 并且c）种子层（3）被转移到热膨胀系数CTE5的支撑衬底（5）上，中间衬底（1）和支撑衬底（5）被选择为使得A1n和CTE11> An和CTE1 = CTE3和CTE5

公开(公告)号：WO2010099837A1

公开(公告)日：2010-09-10

申请号：PCT/EP2009/061711

申请日：2009-09-09

Applicant: S.O.I.TEC SILICON ON INSULATOR TECHNOLOGIES ,  KENNARD, Mark

Inventor： KENNARD, Mark

IPC: H01L21/762

CPC classification number: H01L21/76254

Abstract: The invention relates to a method for manufacturing a heterostructure, notably intended for applications in the fields of electronics, photovoltaics, optics or optoelectronics, which comprises the following steps: - implantation of atomic species inside a first so-called "donor" substrate (1), so as to form an embrittlement area (11) therein, - assembly of a second so-called "receiver" substrate (3), on the donor substrate (1), - detachment of the rear portion of said donor substrate (1) along the embrittlement area (11) so as to individualize a thin layer of interest (12) on the receiver substrate, wherein said receiver substrate (3) has a larger thermal expansion coefficient than that of the donor substrate (1), and which applies so-called "detachment" annealing after said assembly and before said detachment, in order to facilitate the latter, characterized by the fact that said detachment annealing comprises simultaneous application: - of a first temperature to the donor substrate (1); - of a second temperature, different from the first, to the receiver substrate (3); these first and second temperatures being selected so as to reduce the tensile stress condition of the donor substrate (1).

Abstract translation: 本发明涉及一种用于制造异质结构的方法，特别适用于电子，光伏，光学或光电子学领域，其包括以下步骤：将原子物质植入第一所谓的“供体”衬底（1 ），以在其中形成脆化区域（11）， - 在施主衬底（1）上组装第二所谓的“接收器”衬底（3）， - 将所述供体衬底（1）的后部分离 沿着脆化区域（11），以便将感兴趣的薄层（12）个体化在接收器基板上，其中所述接收器基板（3）具有比施主基板（1）更大的热膨胀系数，并且其中 在所述组装之后和在所述分离之前，在所述分离之后应用所谓的“脱离”退火，以便于后者，其特征在于所述脱离退火包括同时施加： - 施加到施主衬底的第一温度 1）; - 与第一温度不同的第二温度到接收器基板（3）; 选择这些第一和第二温度以便降低施主衬底（1）的拉伸应力条件。

公开(公告)号：WO2010057941A1

公开(公告)日：2010-05-27

申请号：PCT/EP2009/065440

申请日：2009-11-19

Applicant: S.O.I.TEC SILICON ON INSULATOR TECHNOLOGIES ,  GAUDIN, Gweltaz ,  VAUFREDAZ, Alexandre ,  GUITTARD, Fleur

Inventor： GAUDIN, Gweltaz ,  VAUFREDAZ, Alexandre ,  GUITTARD, Fleur

IPC: H01L21/762

CPC classification number: H01L21/76256 ,  H01L21/2007

Abstract: The invention provides a method of producing a heterostructure of the silicon-on-sapphire type, comprising bonding an SOI substrate (110) onto a sapphire substrate (120) and thinning the SOI substrate, thinning being carried out by grinding followed by etching of the SOI substrate (110). In accordance with the method, grinding is carried out using a wheel (210) with a grinding surface (211) that comprises abrasive particles having a mean dimension of more than 6.7 urn; further, after grinding and before etching, said method comprises a step of post-grinding annealing of the heterostructure carried out at a temperature in the range 150 °C to 170 °C.

Abstract translation: 本发明提供了一种制造蓝宝石型的异质结构的方法，包括将SOI衬底（110）接合到蓝宝石衬底（120）上并使SOI衬底变薄，通过研磨进行稀化，然后蚀刻 SOI衬底（110）。 根据该方法，使用具有包括平均尺寸大于6.7μm的磨料颗粒的研磨表面（211）的轮（210）进行研磨; 此外，在研磨之后和蚀刻之前，所述方法包括在150℃至170℃的温度范围内对异质结构进行后磨削退火的步骤。

公开(公告)号：WO2010049497A1

公开(公告)日：2010-05-06

申请号：PCT/EP2009/064308

申请日：2009-10-29

Applicant: S.O.I.TEC SILICON ON INSULATOR TECHNOLOGIES ,  LANDRU, Didier ,  RADU, Ionut ,  VINCENT, Sébastien

Inventor： LANDRU, Didier ,  RADU, Ionut ,  VINCENT, Sébastien

IPC: H01L21/762

CPC classification number: H01L21/187 ,  H01L21/76251

Abstract: The invention relates to a method for producing UTBOX type structures comprising: a) the assembly of a substrate, known as "donor" substrate (1), with a substrate, known as "receiver" substrate (2), at least one of the two substrates comprising an insulating layer (3) of thickness less than 50 nm, b) a first heat treatment for reinforcing the assembly between the two substrates, at temperature below 400°C, carried out during the assembly and/or after assembly, to reinforce said assembly, c) a second heat treatment at temperature above 900°C, the exposure time between 400°C and 900°C being less than 1 minute or 30 seconds.

Abstract translation: 本发明涉及一种用于生产UTBOX型结构的方法，包括：a）将称为“供体”衬底（1）的衬底与称为“接收器”衬底（2）的衬底的组装，至少一个 包括厚度小于50nm的绝缘层（3）的两个基板，b）在组装和/或组装之后执行的在低于400℃的温度下加强两个基板之间的组件的第一热处理， 加强所述组件，c）在高于900℃的温度下的第二次热处理，400℃和900℃之间的曝光时间小于1分钟或30秒。