公开(公告)号：WO1997002594A1

公开(公告)日：1997-01-23

申请号：PCT/US1996011184

申请日：1996-07-01

Applicant: INTEL CORPORATION ,  THOMPSON, Scott ,  BOHR, Mark, T. ,  PACKAN, Paul, A.

Inventor： INTEL CORPORATION

IPC: H01L21/385

CPC classification number: H01L29/6659 ,  H01L21/2257 ,  H01L21/823814 ,  H01L29/6656

Abstract: A process for fabricating a source and drain region which includes a more lightly doped source and drain tip region (40) immediately adjacent to the gate (11) and a more heavily doped main portion (41) of the source and drain region spaced apart from the gate. A first layer (16) of glass (2 % BSG) is used to provide the source of doping for the tip region and a second layer (35) of glass (6 % BSG) is used to provide the dopant for the more heavily doped major portion of source and drain regions. Spacers (30, 31) are formed between the glass layers to define the tip region from the main portion of the source and drain regions.

Abstract translation: 一种用于制造源极和漏极区域的工艺，其包括与栅极（11）紧邻的更轻掺杂的源极和漏极尖端区域（40），以及与源极和漏极区域间隔开的更重掺杂的主要部分（41） 大门。 使用玻璃（2％BSG）的第一层（16）提供尖端区域的掺杂源，并且使用玻璃（6％BSG）的第二层（35）提供掺杂剂用于更重掺杂 源区和漏区的主要部分。 在玻璃层之间形成间隔物（30,31），以从源区和漏区的主要部分限定尖端区域。

公开(公告)号：WO1997013273A1

公开(公告)日：1997-04-10

申请号：PCT/US1996016002

申请日：1996-10-03

Applicant: INTEL CORPORATION ,  THOMPSON, Scott, E. ,  JAN, Chia-Hong ,  PACKAN, Paul, A. ,  GHANI, Tahir ,  ANDIDEH, Ebrahim ,  MOGHADAM, Farhad, K. ,  BOHR, Mark, T.

Inventor： INTEL CORPORATION

IPC: H01L21/385

CPC classification number: H01L29/6659 ,  H01L21/2255 ,  H01L21/823814 ,  H01L29/6656

Abstract: A process for fabricating a source and drain region which includes a more lightly doped source and drain tip region immediately adjacent to the gate and a more heavily doped main portion of the source and drain region spaced apart from the gate. A first layer (16) of glass (2 % BSG) is used to provide the source of doping for the tip region and a second layer (35) of glass (6 % BSG) is used to provide the dopant for the more heavily doped major portion of source and drain regions. Spacers (31) are formed between the glass layers to define the tip region from the main portion of the source and drain regions.

Abstract translation: 一种用于制造源极和漏极区的工艺，其包括与栅极紧邻的更轻掺杂的源极和漏极尖端区域以及与栅极间隔开的源极和漏极区域的更重掺杂的主要部分。 玻璃（2％BSG）的第一层（16）用于为尖端区域提供掺杂源，并且使用第二层玻璃（35％）的玻璃（6％BSG）为掺杂剂提供更高掺杂 源和漏区域的主要部分。 在玻璃层之间形成间隔物（31），以限定来自源极和漏极区域的主要部分的尖端区域。

公开(公告)号：WO0245156A3

公开(公告)日：2003-01-23

申请号：PCT/US0144162

申请日：2001-11-06

Applicant: INTEL CORP ,  ARMSTRONG MARK ,  SCHROM GERHARD ,  KUHN KELIN J ,  PACKAN PAUL A ,  TYAGI SUNIT D ,  THOMPSON SCOTT E

Inventor： ARMSTRONG MARK ,  SCHROM GERHARD ,  KUHN KELIN J ,  PACKAN PAUL A ,  TYAGI SUNIT D ,  THOMPSON SCOTT E

IPC: H01L21/8238 ,  H01L27/092 ,  H01L29/04 ,  H01L29/10 ,  H01L29/78

CPC classification number: H01L29/7846 ,  H01L21/823807 ,  H01L27/092 ,  H01L29/045 ,  H01L29/1033 ,  H01L29/78 ,  H01L29/7843

Abstract: Complementary metal oxide semiconductor transistors are formed on a silicon substrate. The substrate has a {100} crystallographic orientation. The transistors are formed on the substrate so that current flows in the channels of the transistors are parallel to the direction. Additionally, longitudinal tensile stress is applied to the channels.

Abstract translation: 互补金属氧化物半导体晶体管形成在硅衬底上。 基板具有{100}晶体取向。 晶体管形成在衬底上，使得电流在晶体管的沟道中流动平行于<100>方向。 此外，纵向拉伸应力施加到通道。

公开(公告)号：WO2015099782A1

公开(公告)日：2015-07-02

申请号：PCT/US2013/078095

申请日：2013-12-27

Applicant: INTEL CORPORATION ,  PATEL, Pratik ,  LIU, Mark, Y. ,  WIEDEMER, Jami, A. ,  PACKAN, Paul, A.

Inventor： PATEL, Pratik ,  LIU, Mark, Y. ,  WIEDEMER, Jami, A. ,  PACKAN, Paul, A.

IPC: H01L21/336

CPC classification number: H01L29/7848 ,  H01L21/2253 ,  H01L21/324 ,  H01L29/0847 ,  H01L29/24 ,  H01L29/267 ,  H01L29/66492 ,  H01L29/66636 ,  H01L29/66795 ,  H01L29/66803 ,  H01L29/785 ,  H01L29/7851

Abstract: A method including forming an opening in a junction region of a fin on and extending from a substrate; introducing a doped semiconductor material in the opening; and thermal processing the doped semiconductor material. A method including forming a gate electrode on a fin extending from a substrate; forming openings in the fin adjacent opposite sides of the gate electrode; introducing a doped semiconductor material in the openings; and thermally processing the doped semiconductor material sufficient to induce the diffusion of a dopant in the doped semiconductor material. An apparatus including a gate electrode transversing a fin extending from a substrate; and semiconductor material filled openings injunction regions of the fin adjacent opposite sides of the gate electrode, wherein the semiconductor material comprises a dopant.

Abstract translation: 一种方法，包括在鳍片的接合区域中形成开口并在基底上延伸的方法; 在开口中引入掺杂的半导体材料; 并对掺杂的半导体材料进行热处理。 一种方法，包括在从衬底延伸的翅片上形成栅电极; 在所述鳍片的邻近的所述栅电极的相对侧上形成开口; 在开口中引入掺杂的半导体材料; 并且热处理足以引起掺杂半导体材料中的掺杂剂扩散的掺杂​​半导体材料。 一种装置，包括横跨从基板延伸的翅片的栅电极; 以及半导体材料填充的栅电极相邻相对侧的翅片的禁止区域，其中半导体材料包括掺杂剂。