公开(公告)号：WO2011163169A1

公开(公告)日：2011-12-29

申请号：PCT/US2011/041165

申请日：2011-06-21

Applicant: SUVOLTA, INC. ,  SHIFREN, Lucian ,  RANADE, Pushkar ,  GREGORY, Paul, E. ,  SONKUSALE, Sachin, R. ,  ZHANG, Weimin ,  THOMPSON, Scott, E.

Inventor： SHIFREN, Lucian ,  RANADE, Pushkar ,  GREGORY, Paul, E. ,  SONKUSALE, Sachin, R. ,  ZHANG, Weimin ,  THOMPSON, Scott, E.

IPC: G05F1/10 ,  H01L29/78

CPC classification number: H01L29/1083 ,  H01L21/823412 ,  H01L21/82345 ,  H01L21/823493 ,  H01L27/088 ,  H01L27/092 ,  H01L29/0847 ,  H01L29/1033 ,  H01L29/1045 ,  H01L29/36 ,  H01L29/66537 ,  H01L29/78 ,  H01L29/7816 ,  H01L29/7833 ,  H01L29/7836

Abstract: An advanced transistor with punch through suppression includes a gate with length Lg, a well doped to have a first concentration of a dopant, and a screening region positioned under the gate and having a second concentration of dopant. The second concentration of dopant may be greater than 5 x 10 dopant atoms per cm. At least one punch through suppression region is disposed under the gate between the screening region and the well. The punch through suppression region has a third concentration of a dopant intermediate between the first concentration and the second concentration of dopant. A bias voltage may be applied to the well region to adjust a threshold voltage of the transistor.

Abstract translation: 具有穿通抑制的高级晶体管包括具有长度为Lg的阱，阱掺杂以具有掺杂剂的第一浓度，以及位于栅极下方并具有第二掺杂浓度的屏蔽区域。 掺杂剂的第二浓度可以大于每厘米5×10个掺杂剂原子。 在筛选区域和井之间的栅极下方设置有至少一个穿孔抑制区域。 穿通抑制区域具有在第一浓度和第二浓度掺杂剂之间的掺杂剂的第三浓度。 可以将偏置电压施加到阱区域以调整晶体管的阈值电压。

公开(公告)号：WO2011163164A1

公开(公告)日：2011-12-29

申请号：PCT/US2011/041156

申请日：2011-06-21

Applicant: SUVOLTA, INC. ,  SHIFREN, Lucian ,  RANADE, Pushkar ,  SCUDDER, Lance ,  THOMPSON, Scott, E.

Inventor： SHIFREN, Lucian ,  RANADE, Pushkar ,  SCUDDER, Lance ,  THOMPSON, Scott, E.

IPC: H01L29/10 ,  H01L29/36 ,  H01L29/78

CPC classification number: H01L21/823412 ,  H01L21/265 ,  H01L21/82345 ,  H01L21/823493 ,  H01L27/088 ,  H01L29/1083 ,  H01L29/66537 ,  H01L29/7836

Abstract: An advanced transistor with threshold voltage set dopant structure includes a gate with length Lg and a well doped to have a first concentration of a dopant. A screening region is positioned between the well and the gate and has a second concentration of dopant greater than 5 x 10 18 dopant atoms per cm 3 . A threshold voltage set region is formed by placement of a threshold voltage offset plane positioned above the screening region. The threshold voltage set region may be formed by delta doping and have a thickness between Lg/5 and Lg/1. The structure uses minimal or no halo implants to maintain channel dopant concentration at less than 5 x 10 17 dopant atoms per cm 3 .

Abstract translation: 具有阈值电压设置掺杂剂结构的高级晶体管包括具有长度Lg的阱，并且阱掺杂以具有掺杂剂的第一浓度。 筛选区域位于阱和栅极之间，并且具有大于每立方厘米5×1018个掺杂剂原子的第二浓度的掺杂剂。 通过放置位于筛选区域上方的阈值电压偏移平面来形成阈值电压设定区域。 阈值电压设定区域可以通过δ掺杂形成，并具有Lg / 5和Lg / 1之间的厚度。 该结构使用最小或无晕轮植入物来保持沟道掺杂剂浓度小于每立方厘米5×1017个掺杂剂原子。

公开(公告)号：WO2011062789A1

公开(公告)日：2011-05-26

申请号：PCT/US2010/055762

申请日：2010-11-08

Applicant: SUVOLTA, INC. ,  THOMPSON, Scott, E. ,  THUMMALAPALLY, Damodar, R.

Inventor： THOMPSON, Scott, E. ,  THUMMALAPALLY, Damodar, R.

IPC: H01L29/02

CPC classification number: H01L21/823807 ,  H01L21/26513 ,  H01L21/823892 ,  H01L27/0207 ,  H01L27/092 ,  H01L29/105 ,  H01L29/1083 ,  H01L29/66636 ,  H01L29/7834

Abstract: A suite of novel structures and methods is provided to reduce power consumption in a wide array of electronic devices and systems Some of these structures and methods can be implemented largely by reusing existing bulk CMOS process flows and manufacturing technology, allowing the semiconductor industry as well as the broader electronics industry to avoid a costly and risky switch to alternative technologies As will be discussed, some of the structures and methods relate to a Deeply Depleted Channel (DDC) design, allowing CMOS based devices to have a reduced sigma VT compared to conventional bulk CMOS and can allow the threshold voltage VT of FETs having dopants in the channel region to be set much more precisely The DDC design also can have a strong body effect compared to conventional bulk CMOS transistors, which can allow for significant dynamic control of power consumption in DDC transistors

Abstract translation: 提供了一套新颖的结构和方法来减少广泛的电子设备和系统的功耗。这些结构和方法中的一些可以通过重用现有的大量CMOS工艺流程和制造技术来实现，这允许半导体工业以及 更广泛的电子工业，以避免成本高昂的风险转换到替代技术如将讨论的，一些结构和方法涉及深度消耗通道（DDC）设计，允许基于CMOS的器件与常规体积相比具有降低的sigma VT CMOS，并且可以允许在沟道区域中具有掺杂剂的FET的阈值电压VT被更精确地设置。与常规体CMOS晶体管相比，DDC设计还可以具有强的体效应，这可以允许对功率消耗的显着动态控制 DDC晶体管

公开(公告)号：WO2013022753A3

公开(公告)日：2013-02-14

申请号：PCT/US2012/049531

申请日：2012-08-03

Applicant: HOFFMANN, Thomas ,  THOMPSON, Scott, E. ,  SUVOLTA, INC.

Inventor： HOFFMANN, Thomas ,  THOMPSON, Scott, E.

IPC: H01L29/78 ,  H01L21/336

Abstract: A method of fabricating semiconductor devices includes providing a semiconducting substrate. The method also includes defining a heavily doped region at a surface of the semiconducting substrate in at least one area of the semiconducting substrate, where the heavily doped region includes a heavily doped layer having a doping concentration greater than a doping concentration of the semiconducting substrate. The method also includes forming an additional layer of semiconductor material on the semiconducting substrate, the additional layer comprising a substantially undoped layer. The method further includes applying a first removal process to the semiconducting substrate to define an unetched portion and an etched portion, where the unetched portion defines a fin structure, and the etched portion extends through the additional layer, and then isolating the fin structure from other structures.

公开(公告)号：WO2011103318A1

公开(公告)日：2011-08-25

申请号：PCT/US2011/025284

申请日：2011-02-17

Applicant: SUVOLTA, INC. ,  THOMPSON, Scott, E. ,  THUMMALAPALLY, Damodar, R.

Inventor： THOMPSON, Scott, E. ,  THUMMALAPALLY, Damodar, R.

IPC: H01L29/76

CPC classification number: H01L29/1083 ,  H01L21/0262 ,  H01L21/26513 ,  H01L21/823412 ,  H01L21/823481 ,  H01L21/823493 ,  H01L21/823807 ,  H01L21/823892 ,  H01L21/84 ,  H01L27/0207 ,  H01L27/0921 ,  H01L27/11 ,  H01L27/1104 ,  H01L29/0653 ,  H01L29/105 ,  H01L29/1079 ,  H01L29/66545 ,  H01L29/66568 ,  H01L29/66628 ,  H01L29/7834 ,  H01L29/7838

Abstract: A suite of novel structures and methods is provided to reduce power consumption in a wide array of electronic devices and systems. Some of these structures and methods can be implemented largely by reusing existing bulk CMOS process flows and manufacturing technology, allowing the semiconductor industry as well as the broader electronics industry to avoid a costly and risky switch to alternative technologies. As will be discussed, some of the structures and methods relate to a Deeply Depleted Channel (DDC) design, allowing CMOS based devices to have a reduced aV'r compared to conventional bulk CMOS and can allow the threshold voltage V T of FETs having dopants in the channel region to be set much more precisely. The DDC design also can have a strong body effect compared to conventional bulk CMOS transistors, which can allow for significant dynamic control of power consumption in DDC transistors.

Abstract translation: 提供了一套新颖的结构和方法，以减少广泛的电子设备和系统的功耗。 这些结构和方法中的一些可以通过重用现有的大量CMOS工艺流程和制造技术来实现，从而允许半导体行业以及更广泛的电子行业避免代替替代技术的成本高昂的风险。 如将要讨论的那样，一些结构和方法涉及深度消耗通道（DDC）设计，允许基于CMOS的器件与常规体CMOS相比具有减小的aV'，并且可以允许具有掺杂剂的FET的阈值电压VT 要更精确地设置通道区域。 与传统的体积CMOS晶体管相比，DDC设计也可以具有强大的机身效应，可以显着地动态控制DDC晶体管的功耗。

公开(公告)号：WO2011041110A1

公开(公告)日：2011-04-07

申请号：PCT/US2010/049000

申请日：2010-09-15

Applicant: SUVOLTA, INC. ,  THOMPSON, Scott, E. ,  THUMMALAPALLY, Damodar, R.

Inventor： THOMPSON, Scott, E. ,  THUMMALAPALLY, Damodar, R.

IPC: H01L21/335

CPC classification number: H01L21/823412 ,  H01L21/823493 ,  H01L21/84 ,  H01L27/0207 ,  H01L27/11 ,  H01L27/1104 ,  H01L29/105 ,  H01L29/1079 ,  H01L29/66545 ,  H01L29/66628 ,  H01L29/7834

Abstract: A suite of novel structures and methods is provided to reduce power consumption in a wide array of electronic devices and systems Some structures and methods can be implemented largely by reusing existing bulk CMOS process flows and manufacturing technology, allowing the semiconductor industry as well as the broader electronics industry to avoid a costly and nsky switch to alternative technologies Some structures and methods relate to a Deeply Depleted Channel (DDC) design, allowing CMOS based devices to have a reduced oVT compared to conventional bulk CMOS and can allow the threshold voltage VT ofFETs having dopants in the channel region to be set more precisely The DDC design also can have a strong body effect compared to conventional bulk CMOS transistors, which can allow for significant dynamic control of power consumption in DDC transistors There are many ways to configure the DDC to achieve different benefits

Abstract translation: 提供了一套新颖的结构和方法，以减少广泛的电子设备和系统的功耗。一些结构和方法可以通过重用现有的大容量CMOS工艺流程和制造技术来实现，从而允许半导体工业以及更广泛的 电子工业，以避免昂贵的和非法的转换到替代技术一些结构和方法涉及深度消耗通道（DDC）设计，允许基于CMOS的器件与常规体CMOS相比具有降低的oVT，并且可以允许FET的阈值电压VT具有 沟道区域中的掺杂剂要更精确地设置DDC设计与常规体CMOS晶体管相比可以具有强大的机体效应，这可以使DDC晶体管的功耗显着动态控制有很多种配置DDC的方法可以实现 不同的好处

公开(公告)号：WO0245156A3

公开(公告)日：2003-01-23

申请号：PCT/US0144162

申请日：2001-11-06

Applicant: INTEL CORP ,  ARMSTRONG MARK ,  SCHROM GERHARD ,  KUHN KELIN J ,  PACKAN PAUL A ,  TYAGI SUNIT D ,  THOMPSON SCOTT E

Inventor： ARMSTRONG MARK ,  SCHROM GERHARD ,  KUHN KELIN J ,  PACKAN PAUL A ,  TYAGI SUNIT D ,  THOMPSON SCOTT E

IPC: H01L21/8238 ,  H01L27/092 ,  H01L29/04 ,  H01L29/10 ,  H01L29/78

CPC classification number: H01L29/7846 ,  H01L21/823807 ,  H01L27/092 ,  H01L29/045 ,  H01L29/1033 ,  H01L29/78 ,  H01L29/7843

Abstract: Complementary metal oxide semiconductor transistors are formed on a silicon substrate. The substrate has a {100} crystallographic orientation. The transistors are formed on the substrate so that current flows in the channels of the transistors are parallel to the direction. Additionally, longitudinal tensile stress is applied to the channels.

Abstract translation: 互补金属氧化物半导体晶体管形成在硅衬底上。 基板具有{100}晶体取向。 晶体管形成在衬底上，使得电流在晶体管的沟道中流动平行于<100>方向。 此外，纵向拉伸应力施加到通道。

公开(公告)号：WO2011041109A1

公开(公告)日：2011-04-07

申请号：PCT/US2010/048998

申请日：2010-09-15

Applicant: SUVOLTA, INC. ,  THOMPSON, Scott, E. ,  THUMMALAPALLY, Damodar, R.

Inventor： THOMPSON, Scott, E. ,  THUMMALAPALLY, Damodar, R.

IPC: H01L21/336

CPC classification number: H01L21/823412 ,  H01L21/823493 ,  H01L21/84 ,  H01L27/0207 ,  H01L27/11 ,  H01L27/1104 ,  H01L29/105 ,  H01L29/1079 ,  H01L29/66545 ,  H01L29/66628 ,  H01L29/7834

Abstract: A system and method to reduce power consumption in electronic devices is disclosed. The structures and methods can be implemented largely by reusing bulk CMOS process flows and manufacturing technology. The structures and methods relate to a Deeply Depleted Channel (DDC) design, allowing CMOS based devices to have a reduced sigma VT compared to conventional bulk CMOS and can allow the threshold voltage VT of FETs having dopants in the channel region to be set more precisely. The DDC design also has a strong body effect compared to conventional bulk CMOS transistors, which can allow for significant dynamic control of power consumption.

Abstract translation: 公开了一种降低电子设备功耗的系统和方法。 结构和方法可以通过重用批量CMOS工艺流程和制造技术来实现。 结构和方法涉及深度消耗通道（DDC）设计，允许基于CMOS的器件与常规体CMOS相比具有降低的sigma VT，并且可以允许更精确地设置在沟道区中具有掺杂剂的FET的阈值电压VT 。 与传统的体积CMOS晶体管相比，DDC设计也具有强大的机身效应，可以显着的动态控制功耗。

公开(公告)号：WO2006053213A1

公开(公告)日：2006-05-18

申请号：PCT/US2005/040917

申请日：2005-11-09

Applicant: UNIVERSITY OF FLORIDA RESEARCH FOUNDATION, INC. ,  NISHIDA, Toshikazu ,  THOMPSON, Scott, E. ,  OGDEN, Al ,  WU, Kehuey

Inventor： NISHIDA, Toshikazu ,  THOMPSON, Scott, E. ,  OGDEN, Al ,  WU, Kehuey

IPC: H01L21/322 ,  H01L29/84 ,  H01L23/051

CPC classification number: H01L23/13 ,  H01L23/04 ,  H01L23/562 ,  H01L29/7842 ,  H01L29/84 ,  H01L2924/0002 ,  H01L2924/01079 ,  H01L2924/13091 ,  H01L2924/00

Abstract: A packaged semiconductor device (450) includes a semiconductor chip (400) having at least one selectively thinned substrate (cavity) region (410). A package (460) is provided for mounting, enclosing and electrically connecting the chip (400) to the outside world, and structure for applying external stress (470) to induce strain in the thinned substrate region (410). The external stress is preferably adjustable, such as by varying the gas flow (or a vacuum) applied through a pressure valve.

Abstract translation: 封装的半导体器件（450）包括具有至少一个选择性薄化的衬底（空腔）区域（410）的半导体芯片（400）。 提供了用于将芯片（400）安装，封装和电连接到外界的封装（460），以及用于施加外部应力（470）以在减薄的衬底区域（410）中引起应变的结构。 外部应力优选是可调节的，例如通过改变通过压力阀施加的气流（或真空）。

公开(公告)号：WO1997013273A1

公开(公告)日：1997-04-10

申请号：PCT/US1996016002

申请日：1996-10-03

Applicant: INTEL CORPORATION ,  THOMPSON, Scott, E. ,  JAN, Chia-Hong ,  PACKAN, Paul, A. ,  GHANI, Tahir ,  ANDIDEH, Ebrahim ,  MOGHADAM, Farhad, K. ,  BOHR, Mark, T.

Inventor： INTEL CORPORATION

IPC: H01L21/385

CPC classification number: H01L29/6659 ,  H01L21/2255 ,  H01L21/823814 ,  H01L29/6656

Abstract: A process for fabricating a source and drain region which includes a more lightly doped source and drain tip region immediately adjacent to the gate and a more heavily doped main portion of the source and drain region spaced apart from the gate. A first layer (16) of glass (2 % BSG) is used to provide the source of doping for the tip region and a second layer (35) of glass (6 % BSG) is used to provide the dopant for the more heavily doped major portion of source and drain regions. Spacers (31) are formed between the glass layers to define the tip region from the main portion of the source and drain regions.

Abstract translation: 一种用于制造源极和漏极区的工艺，其包括与栅极紧邻的更轻掺杂的源极和漏极尖端区域以及与栅极间隔开的源极和漏极区域的更重掺杂的主要部分。 玻璃（2％BSG）的第一层（16）用于为尖端区域提供掺杂源，并且使用第二层玻璃（35％）的玻璃（6％BSG）为掺杂剂提供更高掺杂 源和漏区域的主要部分。 在玻璃层之间形成间隔物（31），以限定来自源极和漏极区域的主要部分的尖端区域。