公开(公告)号：WO2009091830A2

公开(公告)日：2009-07-23

申请号：PCT/US2009/031002

申请日：2009-01-14

Applicant: APPLIED MATERIALS, INC. ,  LUO, Qian ,  SUNDARRAJAN, Arvind ,  CHUNG, Hua ,  TANG, Xianmin ,  YU, Jick M. ,  NARASIMHAN, Murali K.

Inventor： LUO, Qian ,  SUNDARRAJAN, Arvind ,  CHUNG, Hua ,  TANG, Xianmin ,  YU, Jick M. ,  NARASIMHAN, Murali K.

IPC: H01L21/3205

CPC classification number: H01L21/76873 ,  C25D5/02 ,  C25D21/12 ,  H01L21/76843 ,  H01L21/76856 ,  H01L21/76862 ,  H01L21/76864 ,  H01L21/76877

Abstract: A method and apparatus for selectively controlling deposition rate of conductive material during an electroplating process. Dopants are predominantly incorporated into a conductive seed layer on field regions of a substrate prior to filling openings in the field regions by electroplating. A substrate is positioned in one or more processing chambers, and barrier and conductive seed layers formed. A dopant precursor is provided to the chamber and ionized, with or without voltage bias. The dopant predominantly incorporates into the conductive seed layer on the field regions. Electrical conductivity of the conductive seed layer on the field regions is reduced relative to that of the conductive seed layer in the openings, resulting in low initial deposition rate of metal on the field regions during electroplating, and little or no void formation in the metal deposited in the openings.

Abstract translation: 一种用于在电镀过程中选择性地控制导电材料的沉积速率的方法和装置。 在通过电镀在场区域中填充开口之前，掺杂剂主要被结合到衬底的场区域上的导电种子层中。 衬底被定位在一个或多个处理室中，形成阻挡层和导电种子层。 在室内提供掺杂剂前体，并且在电压偏置或没有电压偏置的情况下电离。 掺杂剂主要并入到场区域上的导电种子层中。 导电种子层在场区域的电导率相对于开口中的导电种子层的导电率降低，导致电镀期间金属在场区域上的初始沉积速率较低，并且在沉积的金属中很少或没有空隙形成 在开口。

公开(公告)号：WO2012039932A3

公开(公告)日：2012-03-29

申请号：PCT/US2011/050656

申请日：2011-09-07

Applicant: APPLIED MATERIALS, INC. ,  YU, Jick M. ,  TAO, Rong ,  FU, Xinyu

Inventor： YU, Jick M. ,  TAO, Rong ,  FU, Xinyu

IPC: H01L21/28 ,  H01L21/203

Abstract: Methods for forming layers on a substrate having one or more features formed therein are provided herein. In some embodiments, a method for forming layers on a substrate having one or more features formed therein may include depositing a seed layer within the one or more features; and etching the seed layer to remove at least a portion of the seed layer proximate an opening of the feature such that the seed layer comprises a first thickness disposed on a lower portion of a sidewall of the feature proximate a bottom of the feature and a second thickness disposed on an upper portion of the sidewall proximate the opening of the feature and wherein the first thickness is greater than the second thickness.

公开(公告)号：WO2010077875A2

公开(公告)日：2010-07-08

申请号：PCT/US2009/068093

申请日：2009-12-15

Applicant: APPLIED MATERIALS, INC. ,  FU, Xinyu ,  YU, Jick, M.

Inventor： FU, Xinyu ,  YU, Jick, M.

IPC: H01L21/324 ,  H01L21/28

CPC classification number: H01L21/76838 ,  H01L21/76844 ,  H01L21/76855 ,  H01L21/76873 ,  H01L21/76877 ,  H01L21/76883

Abstract: Methods for improving electromigration of copper interconnection structures are provided. In one embodiment, a method of annealing a microelectronic device including forming microelectronic features on a substrate, forming a contact structure over the microelectronic features, and forming a copper interconnection structure over the contact structure. A passivation layer is deposited over the copper interconnection structure and the substrate is subjected to a first anneal at a temperature of about 350 C to 400 C for a time duration between about 30 minutes to about 1 hour. The substrate is subjected to a second anneal at a temperature of about 150 C to 300 C for a time duration between about 24 to about 400 hours.

Abstract translation: 提供了改善铜互连结构电迁移的方法。 在一个实施例中，一种退火微电子器件的方法，包括在衬底上形成微电子特征，在微电子特征上形成接触结构，以及在接触结构上形成铜互连结构。 在铜互连结构上沉积钝化层，并且将衬底在约350℃至400℃的温度下进行约30分钟至约1小时的持续时间的第一次退火。 将衬底在约150℃至300℃的温度下进行约24至约400小时的持续时间的第二次退火。

公开(公告)号：WO2009108488A1

公开(公告)日：2009-09-03

申请号：PCT/US2009/033673

申请日：2009-02-10

Applicant: APPLIED MATERIALS, INC. ,  YU, Jick M. ,  WANG, Wei D. ,  WANG, Rongjun ,  CHUNG, Hua

Inventor： YU, Jick M. ,  WANG, Wei D. ,  WANG, Rongjun ,  CHUNG, Hua

IPC: H01L21/28

CPC classification number: H01L21/76879 ,  C25D5/02 ,  H01L21/76856 ,  H01L21/76859 ,  H01L21/76862 ,  H01L21/76873

Abstract: Methods of controlling deposition of metal on field regions of a substrate in an electroplating process are provided. In one aspect, a dielectric layer is deposited under plasma on the field region of a patterned substrate, leaving a conductive surface exposed in the openings. Electroplating on the field region is reduced or eliminated, resulting in void-free features and minimal excess plating. In another aspect, a resistive layer, which may be a metal, is used in place of the dielectric. In a further aspect, the surface of the conductive field region is modified to change its chemical potential relative to the sidewalls and bottoms of the openings.

Abstract translation: 提供了在电镀工艺中控制金属在基片的场区上沉积的方法。 在一个方面，电介质层在等离子体上沉积在图案化衬底的场区上，留下在开口中暴露的导电表面。 场区域上的电镀被减少或消除，导致无空隙特征和最小的多余电镀。 在另一方面，可以使用可以是金属的电阻层来代替电介质。 在另一方面，导电场区的表面被修改以相对于开口的侧壁和底部改变其化学势。

公开(公告)号：WO2008027186A3

公开(公告)日：2008-03-06

申请号：PCT/US2007/017967

申请日：2007-08-14

Applicant: APPLIED MATERIALS, INC. ,  WANG, Rongjun ,  CHUNG, Hua ,  TANG, Xianmin ,  WANG, Jenn, Yue ,  WANG, Wei, D. ,  TANAKA, Yoichiro ,  YU, Jick, M. ,  GOPALRAJA, Praburam

Inventor： WANG, Rongjun ,  CHUNG, Hua ,  TANG, Xianmin ,  WANG, Jenn, Yue ,  WANG, Wei, D. ,  TANAKA, Yoichiro ,  YU, Jick, M. ,  GOPALRAJA, Praburam

IPC: C23C14/34 ,  H01L21/302

Abstract: A fabrication method and a product for the deposition of a conductive barrier or other liner layer in a vertical electrical interconnect structure. One embodiment includes within a hole (88) through a dielectric layer (86) a barrier layer (132) of RuTaN, an adhesion layer (112) of RuTa, and a copper seed layer (114) forming a liner for electroplating of copper. The ruthenium content is preferably greater than 50 at% and more preferably at least 80 at% but less than 95 at%. The barrier and adhesion layers may both be sputter deposited. Other platinum-group elements substitute for the ruthenium and other refractory metals substitute for the tantalum. Aluminum alloying into RuTa (192, 194) when annealed presents a moisture barrier. Copper contacts (232, 238) include different alloying fractions of RuTa to shift the work function to the doping type of the silicon (216, 218).

公开(公告)号：WO2012064925A3

公开(公告)日：2012-07-05

申请号：PCT/US2011060115

申请日：2011-11-10

Applicant: APPLIED MATERIALS INC ,  FU XINYU ,  YU JICK M

Inventor： FU XINYU ,  YU JICK M

IPC: H01L21/28

CPC classification number: H01L23/53233 ,  H01L21/76831 ,  H01L21/76843 ,  H01L21/76849 ,  H01L21/76855 ,  H01L21/76867 ,  H01L21/76877 ,  H01L23/53238 ,  H01L2924/0002 ,  H01L2924/00

Abstract: Methods for forming interconnect or interconnections on a substrate for use in a microelectric device are disclosed. In one or more embodiments, the method includes depositing an alloy layer comprising Cu and an alloying element, for, example, Mn, in a dielectric layer and segregating or diffusing the alloying element from the bulk Cu portion of the alloy layer. In one or more embodiments, the method includes annealing the alloy layer in an atomic hydrogen atmosphere. After annealing, the alloy layer exhibits a resistivity that is substantially equivalent to the resistivity of a pure Cu layer.

Abstract translation: 公开了在用于微电子器件的衬底上形成互连或互连的方法。 在一个或多个实施例中，该方法包括在电介质层中沉积包含Cu和合金元素（例如Mn）的合金层，并将合金元素与合金层的本体Cu部分分离或扩散。 在一个或多个实施例中，该方法包括在原子氢气氛中退火合金层。 退火后，合金层的电阻率基本上等于纯Cu层的电阻率。

公开(公告)号：WO2008027186A2

公开(公告)日：2008-03-06

申请号：PCT/US2007017967

申请日：2007-08-14

Applicant: APPLIED MATERIALS INC ,  WANG RONGJUN ,  CHUNG HUA ,  TANG XIANMIN ,  WANG JENN YUE ,  WANG WEI D ,  TANAKA YOICHIRO ,  YU JICK M ,  GOPALRAJA PRABURAM

Inventor： WANG RONGJUN ,  CHUNG HUA ,  TANG XIANMIN ,  WANG JENN YUE ,  WANG WEI D ,  TANAKA YOICHIRO ,  YU JICK M ,  GOPALRAJA PRABURAM

IPC: B32B7/00 ,  B05D5/12 ,  B32B3/00 ,  C23C14/00 ,  C23C16/00

CPC classification number: C23C14/046 ,  C23C14/0641 ,  C23C14/165 ,  H01L21/2855 ,  H01L21/76844 ,  H01L21/76846 ,  H01L21/76873 ,  H01L23/53238 ,  H01L2924/0002 ,  Y10T428/24917 ,  Y10T428/24926 ,  H01L2924/00

Abstract: A fabrication method and a product for the deposition of a conductive barrier or other liner layer in a vertical electrical interconnect structure. One embodiment includes within a hole (88) through a dielectric layer (86) a barrier layer (132) of RuTaN, an adhesion layer (112) of RuTa, and a copper seed layer (114) forming a liner for electroplating of copper. The ruthenium content is preferably greater than 50 at% and more preferably at least 80 at% but less than 95 at%. The barrier and adhesion layers may both be sputter deposited. Other platinum-group elements substitute for the ruthenium and other refractory metals substitute for the tantalum. Aluminum alloying into RuTa (192, 194) when annealed presents a moisture barrier. Copper contacts (232, 238) include different alloying fractions of RuTa to shift the work function to the doping type of the silicon (216, 218).

Abstract translation: 用于在垂直电互连结构中沉积导电屏障或其它衬垫层的制造方法和产品。 一个实施例包括穿过介电层（86）的孔（88）中的RuTaN的阻挡层（132），RuTa的粘合层（112）和形成铜电镀衬垫的铜籽晶层（114）。 钌含量优选大于50原子％，更优选至少80原子％但小于95原子％。 阻挡层和粘附层可以被溅射沉积。 其他铂族元素代替钌和其他难熔金属代替钽。 当退火时，铝合金化成RuTa（192,194）具有防潮层。 铜触点（232,238）包括RuTa的不同合金分数，以将功函数移动到硅的掺杂类型（216,218）。

公开(公告)号：WO2012064925A2

公开(公告)日：2012-05-18

申请号：PCT/US2011/060115

申请日：2011-11-10

Applicant: APPLIED MATERIALS, INC. ,  FU, Xinyu ,  YU, Jick M.

Inventor： FU, Xinyu ,  YU, Jick M.

IPC: H01L21/28

CPC classification number: H01L23/53233 ,  H01L21/76831 ,  H01L21/76843 ,  H01L21/76849 ,  H01L21/76855 ,  H01L21/76867 ,  H01L21/76877 ,  H01L23/53238 ,  H01L2924/0002 ,  H01L2924/00

Abstract: Methods for forming interconnect or interconnections on a substrate for use in a microelectric device are disclosed. In one or more embodiments, the method includes depositing an alloy layer comprising Cu and an alloying element, for, example, Mn, in a dielectric layer and segregating or diffusing the alloying element from the bulk Cu portion of the alloy layer. In one or more embodiments, the method includes annealing the alloy layer in an atomic hydrogen atmosphere. After annealing, the alloy layer exhibits a resistivity that is substantially equivalent to the resistivity of a pure Cu layer.

Abstract translation: 公开了用于在用于微电器件的衬底上形成互连或互连的方法。 在一个或多个实施例中，该方法包括在电介质层中沉积包含Cu和合金元素（例如Mn）的合金层，并且将合金元素从合金层的块Cu部分分离或扩散。 在一个或多个实施例中，该方法包括在原子氢气氛中对合金层进行退火。 退火后，合金层显示的电阻率基本上等于纯Cu层的电阻率。

公开(公告)号：WO2012039932A2

公开(公告)日：2012-03-29

申请号：PCT/US2011050656

申请日：2011-09-07

Applicant: APPLIED MATERIALS INC ,  YU JICK M ,  TAO RONG ,  FU XINYU

Inventor： YU JICK M ,  TAO RONG ,  FU XINYU

IPC: H01L21/28 ,  H01L21/203

CPC classification number: H01L21/2855 ,  H01L21/76843 ,  H01L21/76865 ,  H01L21/76868 ,  H01L21/76873 ,  H01L21/76879 ,  H01L2221/1089

Abstract: Methods for forming layers on a substrate having one or more features formed therein are provided herein. In some embodiments, a method for forming layers on a substrate having one or more features formed therein may include depositing a seed layer within the one or more features; and etching the seed layer to remove at least a portion of the seed layer proximate an opening of the feature such that the seed layer comprises a first thickness disposed on a lower portion of a sidewall of the feature proximate a bottom of the feature and a second thickness disposed on an upper portion of the sidewall proximate the opening of the feature and wherein the first thickness is greater than the second thickness.

Abstract translation: 本文提供了在其上形成有一个或多个特征的基底上形成层的方法。 在一些实施例中，用于在其上形成有一个或多个特征的衬底上形成层的方法可包括在一个或多个特征内沉积种子层; 并且蚀刻种子层以去除邻近特征的开口的种子层的至少一部分，使得种子层包括设置在靠近特征的底部的特征的侧壁的下部的第一厚度，以及第二 厚度设置在靠近特征开口的侧壁的上部，并且其中第一厚度大于第二厚度。

公开(公告)号：WO2010077875A3

公开(公告)日：2010-09-10

申请号：PCT/US2009068093

申请日：2009-12-15

Applicant: APPLIED MATERIALS INC ,  FU XINYU ,  YU JICK M

Inventor： FU XINYU ,  YU JICK M

IPC: H01L21/324 ,  H01L21/28

CPC classification number: H01L21/76838 ,  H01L21/76844 ,  H01L21/76855 ,  H01L21/76873 ,  H01L21/76877 ,  H01L21/76883

Abstract: Methods for improving electromigration of copper interconnection structures are provided. In one embodiment, a method of annealing a microelectronic device including forming microelectronic features on a substrate, forming a contact structure over the microelectronic features, and forming a copper interconnection structure over the contact structure. A passivation layer is deposited over the copper interconnection structure and the substrate is subjected to a first anneal at a temperature of about 350 C to 400 C for a time duration between about 30 minutes to about 1 hour. The substrate is subjected to a second anneal at a temperature of about 150 C to 300 C for a time duration between about 24 to about 400 hours.

Abstract translation: 提供了用于改善铜互连结构的电迁移的方法。 在一个实施例中，一种退火微电子器件的方法，包括：在衬底上形成微电子特征;在微电子特征上形成接触结构;以及在接触结构上形成铜互连结构。 在铜互连结构上沉积钝化层，并且衬底在大约350℃至400℃的温度下进行第一次退火持续约30分钟至约1小时的时间。 衬底在约150℃至300℃的温度下进行第二次退火持续约24至约400小时的时间。