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    METHODS FOR FORMING INTERCONNECT STRUCTURES
    2.
    发明申请
    METHODS FOR FORMING INTERCONNECT STRUCTURES 审中-公开
    形成互连结构的方法

    公开(公告)号：WO2011156349A3

    公开(公告)日：2012-04-05

    申请号：PCT/US2011039414

    申请日：2011-06-07

    Applicant: APPLIED MATERIALS INC ,  LEE JOUNG JOO ,  TANG XIANMIN ,  GUNG TZA-JING

    Inventor： LEE JOUNG JOO ,  TANG XIANMIN ,  GUNG TZA-JING

    IPC: H01L21/28 ,  H01L21/3205

    CPC classification number: H01L21/2855 ,  C23C14/046 ,  C23C14/345 ,  C23C14/3492 ,  H01L21/76882

    Abstract: Methods for forming interconnect structures are provided herein. In some embodiments, a method for forming an interconnect on a substrate may include depositing a material atop an upper surface of the substrate and atop one or more surfaces of a feature disposed in the substrate by a first deposition process that deposits the material at a faster rate on the upper surface than on a bottom surface of the feature; depositing the material atop the upper surface of the substrate and atop one or more surfaces of the feature by a second deposition process that deposits the material at a greater rate on the bottom surface of the feature than on the upper surface of the substrate; and heating the deposited material to draw the deposited material towards the bottom surface of the feature to at least partially fill the feature with the deposited material.

    Abstract translation: 本文提供形成互连结构的方法。 在一些实施例中，用于在衬底上形成互连的方法可以包括在衬底的上表面顶部沉积材料，并且通过第一沉积工艺沉积位于衬底中的特征的一个或多个表面上，所述第一沉积工艺以更快的速度沉积材料 在上表面上比在特征的底表面上的速率; 通过第二沉积工艺将所述材料沉积在所述基底的上表面顶部和所述特征的一个或多个表面上方，所述第二沉积工艺在所述特征的底表面上以比在所述基底的上表面上更大的速率沉积材料; 以及加热沉积的材料以将沉积的材料拉向特征的底表面，以至少部分地用沉积的材料填充该特征。

    PROCESS KIT SHIELD FOR IMPROVED PARTICLE REDUCTION
    3.
    发明申请
    PROCESS KIT SHIELD FOR IMPROVED PARTICLE REDUCTION 审中-公开
    用于改善颗粒减少的工艺套件

    公开(公告)号：WO2011143527A2

    公开(公告)日：2011-11-17

    申请号：PCT/US2011036395

    申请日：2011-05-13

    Applicant: APPLIED MATERIALS INC ,  RASHEED MUHAMMAD ,  WANG RONGJUN ,  LIU ZHENDONG ,  FU XINYU ,  TANG XIANMIN

    Inventor： RASHEED MUHAMMAD ,  WANG RONGJUN ,  LIU ZHENDONG ,  FU XINYU ,  TANG XIANMIN

    IPC: C23C14/34 ,  C23C14/06

    CPC classification number: C23C14/35 ,  C23C14/564 ,  H01J37/32853 ,  H01J37/32871 ,  H01J37/34 ,  H01J37/3411

    Abstract: Apparatus for improved particle reduction are provided herein. In some embodiments, an apparatus may include a process kit shield comprising a one-piece metal body having an upper portion and a lower portion and having an opening disposed through the one-piece metal body, wherein the upper portion includes an opening-facing surface configured to be disposed about and spaced apart from a target of a physical vapor deposition chamber and wherein the opening-facing surface is configured to limit particle deposition on an upper surface of the upper portion of the one-piece metal body during sputtering of a target material from the target of the physical vapor deposition chamber.

    Abstract translation: 本文提供了用于改善颗粒减少的装置。 在一些实施例中，一种装置可以包括一个包括具有上部和下部的一体式金属体的处理套件屏蔽件，并且具有穿过一体式金属体设置的开口，其中，上部包括面向开口的表面 被配置为围绕物理气相沉积室的目标设置并隔开，并且其中所述面向开口的表面构造成在目标溅射期间限制所述一体金属体的上部的上表面上的颗粒沉积 材料从物理气相沉积室的目标。

    LOW RESISTIVITY TUNGSTEN PVD WITH ENHANCED IONIZATION AND RF POWER COUPLING
    7.
    发明申请
    LOW RESISTIVITY TUNGSTEN PVD WITH ENHANCED IONIZATION AND RF POWER COUPLING 审中-公开
    具有增强离子化和射频功率耦合的低电阻TUNGSTEN PVD

    公开(公告)号：WO2011156650A2

    公开(公告)日：2011-12-15

    申请号：PCT/US2011/039867

    申请日：2011-06-09

    Applicant: APPLIED MATERIALS, INC. ,  CAO, Yong ,  TANG, Xianmin ,  GANDIKOTA, Srinivas ,  WANG, Wei D. ,  LIU, Zhendong ,  MORAES, Kevin ,  RASHEED, Muhammad M. ,  NGUYEN, Thanh X. ,  JUPUDI, Ananthkrishna

    Inventor： CAO, Yong ,  TANG, Xianmin ,  GANDIKOTA, Srinivas ,  WANG, Wei D. ,  LIU, Zhendong ,  MORAES, Kevin ,  RASHEED, Muhammad M. ,  NGUYEN, Thanh X. ,  JUPUDI, Ananthkrishna

    IPC: H01L29/78 ,  H01L21/336 ,  H01L29/43

    CPC classification number: H01L21/28079 ,  C23C14/165 ,  C23C14/345 ,  C23C14/35 ,  H01L21/28088 ,  H01L21/2855 ,  H01L29/4966 ,  H01L29/517 ,  H01L29/78

    Abstract: Embodiments described herein provide a semiconductor device and methods and apparatuses of forming the same. The semiconductor device includes a substrate having a source and drain region and a gate electrode stack on the substrate between the source and drain regions. The gate electrode stack includes a conductive film layer on a gate dielectric layer, a refractory metal nitride film layer on the conductive film layer, a silicon-containing film layer on the refractory metal nitride film layer, and a tungsten film layer on the silicon-containing film layer. In one embodiment, the method includes positioning a substrate within a processing chamber, wherein the substrate includes a source and drain region, a gate dielectric layer between the source and drain regions, and a conductive film layer on the gate dielectric layer. The method also includes depositing a refractory metal nitride film layer on the conductive film layer, depositing a silicon-containing film layer on the refractory metal nitride film layer, and depositing a tungsten film layer on the silicon-containing film layer.

    Abstract translation: 本文描述的实施例提供了一种半导体器件及其形成方法和装置。 半导体器件包括在源极和漏极区域之间的衬底上具有源极和漏极区域以及栅电极堆叠的衬底。 栅极电极堆叠包括在栅极电介质层上的导电膜层，导电膜层上的难熔金属氮化物膜层，难熔金属氮化物膜层上的含硅膜层，以及硅 - 含有膜层。 在一个实施例中，该方法包括将衬底定位在处理室内，其中衬底包括源极和漏极区域，源极和漏极区域之间的栅极介电层以及栅极电介质层上的导电膜层。 该方法还包括在导电膜层上沉积难熔金属氮化物膜层，在难熔金属氮化物膜层上沉积含硅膜层，并在含硅膜层上沉积钨膜层。

    CU SURFACE PLASMA TREATMENT TO IMPROVE GAPFILL WINDOW
    10.
    发明申请
    CU SURFACE PLASMA TREATMENT TO IMPROVE GAPFILL WINDOW 审中-公开
    CU表面等离子体处理，以改善GAPFILL WINDOW

    公开(公告)号：WO2009091830A2

    公开(公告)日：2009-07-23

    申请号：PCT/US2009/031002

    申请日：2009-01-14

    Applicant: APPLIED MATERIALS, INC. ,  LUO, Qian ,  SUNDARRAJAN, Arvind ,  CHUNG, Hua ,  TANG, Xianmin ,  YU, Jick M. ,  NARASIMHAN, Murali K.

    Inventor： LUO, Qian ,  SUNDARRAJAN, Arvind ,  CHUNG, Hua ,  TANG, Xianmin ,  YU, Jick M. ,  NARASIMHAN, Murali K.

    IPC: H01L21/3205

    CPC classification number: H01L21/76873 ,  C25D5/02 ,  C25D21/12 ,  H01L21/76843 ,  H01L21/76856 ,  H01L21/76862 ,  H01L21/76864 ,  H01L21/76877

    Abstract: A method and apparatus for selectively controlling deposition rate of conductive material during an electroplating process. Dopants are predominantly incorporated into a conductive seed layer on field regions of a substrate prior to filling openings in the field regions by electroplating. A substrate is positioned in one or more processing chambers, and barrier and conductive seed layers formed. A dopant precursor is provided to the chamber and ionized, with or without voltage bias. The dopant predominantly incorporates into the conductive seed layer on the field regions. Electrical conductivity of the conductive seed layer on the field regions is reduced relative to that of the conductive seed layer in the openings, resulting in low initial deposition rate of metal on the field regions during electroplating, and little or no void formation in the metal deposited in the openings.

    Abstract translation: 一种用于在电镀过程中选择性地控制导电材料的沉积速率的方法和装置。 在通过电镀在场区域中填充开口之前，掺杂剂主要被结合到衬底的场区域上的导电种子层中。 衬底被定位在一个或多个处理室中，形成阻挡层和导电种子层。 在室内提供掺杂剂前体，并且在电压偏置或没有电压偏置的情况下电离。 掺杂剂主要并入到场区域上的导电种子层中。 导电种子层在场区域的电导率相对于开口中的导电种子层的导电率降低，导致电镀期间金属在场区域上的初始沉积速率较低，并且在沉积的金属中很少或没有空隙形成 在开口。

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