公开(公告)号：WO2017034654A1

公开(公告)日：2017-03-02

申请号：PCT/US2016/037690

申请日：2016-06-15

Applicant: APPLE INC.

Inventor： LAI, Kwan-Yu ,  ZHAI, Jun ,  HU, Kunzhong

IPC: H01L23/00 ,  H01L25/065 ,  H01L25/10 ,  H01L25/00 ,  H01L23/498 ,  H01L21/48

CPC classification number: H01L25/0657 ,  H01L21/486 ,  H01L21/568 ,  H01L21/6835 ,  H01L21/7684 ,  H01L23/147 ,  H01L23/3107 ,  H01L23/481 ,  H01L23/49816 ,  H01L23/5384 ,  H01L23/5385 ,  H01L23/5386 ,  H01L23/5389 ,  H01L24/80 ,  H01L24/89 ,  H01L25/0652 ,  H01L25/0655 ,  H01L25/10 ,  H01L25/105 ,  H01L25/50 ,  H01L2221/68327 ,  H01L2224/80895 ,  H01L2224/80896 ,  H01L2225/06541 ,  H01L2225/06548 ,  H01L2924/181 ,  H01L2924/186

Abstract: Packages and 3D die stacking processes are described. In an embodiment, a package includes a second level die hybrid bonded to a first package level including a first level die encapsulated in an oxide layer, and a plurality of through oxide vias (TOVs) extending through the oxide layer. In an embodiment, the TOVs and the first level die have a height of about 20 microns or less.

Abstract translation: 描述了封装和3D裸片堆叠过程。 在一个实施例中，封装包括结合到包括封装在氧化物层中的第一级管芯的第一封装级的第二级管芯晶体管和延伸穿过氧化物层的多个通孔氧化物通孔（TOV）。 在一个实施例中，TOV和第一级模具具有大约20微米或更小的高度。

公开(公告)号：WO2017078849A1

公开(公告)日：2017-05-11

申请号：PCT/US2016/051479

申请日：2016-09-13

Applicant: APPLE INC.

Inventor： HSU, Jun Chung ,  CARSON, Flynn P. ,  LAI, Kwan-Yu

IPC: H01L23/498 ,  H01L21/48 ,  H05K3/46

CPC classification number: H01L21/568 ,  H01L21/4857 ,  H01L21/561 ,  H01L23/3128 ,  H01L23/49822 ,  H01L23/552 ,  H01L24/13 ,  H01L24/16 ,  H01L24/81 ,  H01L24/97 ,  H01L2224/0401 ,  H01L2224/131 ,  H01L2224/16235 ,  H01L2224/16245 ,  H01L2224/81005 ,  H01L2224/97 ,  H01L2924/1431 ,  H01L2924/1434 ,  H01L2924/1461 ,  H01L2924/15311 ,  H01L2924/3025 ,  H05K3/4682 ,  Y10T29/49156 ,  H01L2924/014 ,  H01L2924/00014 ,  H01L2224/81

Abstract: Method of forming ultra thin coreless substrates are described. In an embodiment, the method utilizes a debond layer including high and low adhesion surface areas to the carrier substrate, and cutting through the low adhesion surface areas to remove a build-up structure from the carrier substrate. An electrical short layer may be formed as a part of or on the debond layer to facilitate electrical testing of the build-up structure prior to debonding, and aid in the formation a "known good" substrate on a support substrate.

Abstract translation: 描述了形成超薄无芯基板的方法。 在一个实施例中，该方法利用包括高和低粘附表面区域的剥离层到载体基底，并切割低粘附表面区域以从载体基底去除堆积结构。 电短层可以形成为脱粘层的一部分或在脱粘层上，以便于在脱粘之前对增层结构进行电测试，并有助于形成“已知良好”的结构。 衬底在支撑衬底上。

公开(公告)号：WO2020112505A3

公开(公告)日：2020-06-04

申请号：PCT/US2019/062702

申请日：2019-11-21

Applicant: APPLE INC.

Inventor： DABRAL, Sanjay ,  ZHAI, Jun ,  LAI, Kwan-Yu ,  HU, Kunzhong ,  RAMACHANDRAN, Vidhya

IPC: H01L21/60 ,  H01L23/538 ,  H01L21/56 ,  H01L21/66 ,  H01L23/60 ,  H01L23/29

Abstract: Stitched die packaging techniques and structures are described in which reconstituted chips are formed using wafer reconstitution and die-stitching techniques. In an embodiment, a chip includes a reconstituted chip-level back end of the line (BEOL) build-up structure (310) to connect a die set (110, 110) embedded in an inorganic gap fill material (130).

公开(公告)号：WO2020112505A2

公开(公告)日：2020-06-04

申请号：PCT/US2019/062702

申请日：2019-11-21

Applicant: APPLE INC.

Inventor： DABRAL, Sanjay ,  ZHAI, Jun ,  LAI, Kwan-Yu ,  HU, Kunzhong ,  RAMACHANDRAN, Vidhya

IPC: H01L21/60 ,  H01L23/538 ,  H01L21/56 ,  H01L21/66 ,  H01L23/60

Abstract: Stitched die packaging techniques and structures are described in which reconstituted chips are formed using wafer reconstitution and die-stitching techniques. In an embodiment, a chip includes a reconstituted chip-level back end of the line (BEOL) build-up structure to connect a die set embedded in an inorganic gap fill material.

公开(公告)号：WO2016140819A2

公开(公告)日：2016-09-09

申请号：PCT/US2016/018804

申请日：2016-02-19

Applicant: APPLE INC.

Inventor： ZHAI, Jun ,  HU, Kunzhong ,  LAI, Kwan-Yu ,  PANG, Mengzhi ,  ZHONG, Chonghua ,  YANG, Se Young

IPC: H01L23/31 ,  H01L21/56 ,  H01L23/538

CPC classification number: H01L25/0652 ,  H01L21/568 ,  H01L23/3135 ,  H01L23/49816 ,  H01L23/5383 ,  H01L23/5384 ,  H01L23/5389 ,  H01L24/19 ,  H01L24/96 ,  H01L25/50 ,  H01L2224/04105 ,  H01L2224/08167 ,  H01L2224/12105 ,  H01L2224/131 ,  H01L2224/16227 ,  H01L2224/27318 ,  H01L2224/2732 ,  H01L2224/27436 ,  H01L2224/2919 ,  H01L2224/32225 ,  H01L2224/73267 ,  H01L2224/81193 ,  H01L2224/83191 ,  H01L2224/83855 ,  H01L2224/83862 ,  H01L2224/83874 ,  H01L2224/92244 ,  H01L2224/94 ,  H01L2225/06517 ,  H01L2225/0652 ,  H01L2225/06524 ,  H01L2225/06572 ,  H01L2924/1431 ,  H01L2924/1433 ,  H01L2924/1434 ,  H01L2924/1436 ,  H01L2924/1461 ,  H01L2924/18161 ,  H01L2924/18162 ,  H01L2924/19041 ,  H01L2924/19042 ,  H01L2924/19105 ,  H01L2224/27 ,  H01L2924/014

Abstract: Packages and methods of formation are described. In an embodiment, a system in package (SiP) includes first and second redistribution layers (RDLs), and a plurality of die attached to the front and back side of the first RDL. The first and second RDLs are coupled together with a plurality of conductive pillars extending from the back side of the first RDL to a front side of the second RDL.

Abstract translation: 描述了包装和形成方法。 在一个实施例中，封装系统（SiP）包括第一和第二再分配层（RDL）以及附接到第一RDL的前侧和后侧的多个管芯。 第一和第二RDL与从第一RDL的后侧延伸到第二RDL的前侧的多个导电柱连接在一起。