公开(公告)号：WO2022066364A1

公开(公告)日：2022-03-31

申请号：PCT/US2021/048174

申请日：2021-08-30

Applicant: APPLE INC.

Inventor： DABRAL, Sanjay ,  CAO, Zhitao ,  HU, Kunzhong

IPC: H01L23/538 ,  H01L23/528 ,  H01L23/00

Abstract: Structures and methods of forming fine die-to-die interconnect routing are described. In an embodiment, a package includes a package-level RDL than spans across a die set and includes a plurality of die-to-die interconnects connecting contact pads between each die. In an embodiment, the plurality of die-to-die interconnects is embedded within one or more photoimageable organic dielectric layers.

公开(公告)号：WO2021236396A1

公开(公告)日：2021-11-25

申请号：PCT/US2021/032047

申请日：2021-05-12

Applicant: APPLE INC.

Inventor： CHEN, Wei ,  ZHAI, Jun ,  HU, Kunzhong

IPC: H01L23/10 ,  H01L23/051 ,  H01L25/16

Abstract: Electronic packages and modules are described. In an embodiment, a hybrid thermal interface material including materials with different thermal conductivities is used to attach a lid to a device. In an embodiment, a low temperature solder material is included as part of an adhesion layer for attachment with a stiffener structure.

公开(公告)号：WO2017034654A1

公开(公告)日：2017-03-02

申请号：PCT/US2016/037690

申请日：2016-06-15

Applicant: APPLE INC.

Inventor： LAI, Kwan-Yu ,  ZHAI, Jun ,  HU, Kunzhong

IPC: H01L23/00 ,  H01L25/065 ,  H01L25/10 ,  H01L25/00 ,  H01L23/498 ,  H01L21/48

CPC classification number: H01L25/0657 ,  H01L21/486 ,  H01L21/568 ,  H01L21/6835 ,  H01L21/7684 ,  H01L23/147 ,  H01L23/3107 ,  H01L23/481 ,  H01L23/49816 ,  H01L23/5384 ,  H01L23/5385 ,  H01L23/5386 ,  H01L23/5389 ,  H01L24/80 ,  H01L24/89 ,  H01L25/0652 ,  H01L25/0655 ,  H01L25/10 ,  H01L25/105 ,  H01L25/50 ,  H01L2221/68327 ,  H01L2224/80895 ,  H01L2224/80896 ,  H01L2225/06541 ,  H01L2225/06548 ,  H01L2924/181 ,  H01L2924/186

Abstract: Packages and 3D die stacking processes are described. In an embodiment, a package includes a second level die hybrid bonded to a first package level including a first level die encapsulated in an oxide layer, and a plurality of through oxide vias (TOVs) extending through the oxide layer. In an embodiment, the TOVs and the first level die have a height of about 20 microns or less.

Abstract translation: 描述了封装和3D裸片堆叠过程。 在一个实施例中，封装包括结合到包括封装在氧化物层中的第一级管芯的第一封装级的第二级管芯晶体管和延伸穿过氧化物层的多个通孔氧化物通孔（TOV）。 在一个实施例中，TOV和第一级模具具有大约20微米或更小的高度。

公开(公告)号：WO2016171805A1

公开(公告)日：2016-10-27

申请号：PCT/US2016/021405

申请日：2016-03-08

Applicant: APPLE INC.

Inventor： ZHAI, Jun ,  HU, Kunzhong

IPC: H01L21/60 ,  H01L23/538 ,  H01L25/065

CPC classification number: H01L25/105 ,  H01L21/561 ,  H01L21/568 ,  H01L23/3128 ,  H01L23/3135 ,  H01L23/5389 ,  H01L24/13 ,  H01L24/19 ,  H01L24/20 ,  H01L24/24 ,  H01L24/73 ,  H01L24/82 ,  H01L24/92 ,  H01L24/96 ,  H01L24/97 ,  H01L25/0652 ,  H01L25/0657 ,  H01L25/50 ,  H01L2224/0401 ,  H01L2224/04105 ,  H01L2224/12105 ,  H01L2224/131 ,  H01L2224/16227 ,  H01L2224/16235 ,  H01L2224/16237 ,  H01L2224/24011 ,  H01L2224/24105 ,  H01L2224/24225 ,  H01L2224/32145 ,  H01L2224/32225 ,  H01L2224/73204 ,  H01L2224/73253 ,  H01L2224/73267 ,  H01L2224/81005 ,  H01L2224/82005 ,  H01L2224/82101 ,  H01L2224/82106 ,  H01L2224/83101 ,  H01L2224/83855 ,  H01L2224/83862 ,  H01L2224/83874 ,  H01L2224/92125 ,  H01L2224/92225 ,  H01L2224/92244 ,  H01L2224/96 ,  H01L2224/97 ,  H01L2225/1023 ,  H01L2225/1035 ,  H01L2225/1041 ,  H01L2225/1058 ,  H01L2924/1431 ,  H01L2924/1436 ,  H01L2924/1437 ,  H01L2924/1443 ,  H01L2924/1451 ,  H01L2924/14511 ,  H01L2224/83 ,  H01L2224/82 ,  H01L2224/81 ,  H01L2924/014 ,  H01L2924/00014 ,  H01L2924/00012 ,  H01L2224/19

Abstract: Vertically stacked system in package structures are described. A package includes a first level (125) molding (122) and fan out structure (130), a third level (185) molding (182) and fan out structure (190) and a second level (155) molding (152) and fan out structure (160) between the first and third levels (125, 185). The first level (125) molding (122) and fan out structure (130) includes a first level die (110), the second level (155) molding (152) and fan out structure (160) includes back-to-back facing dies (142), with a front surface of each die (142) bonded to a redistribution layer (130, 160), and the third level (185) molding (182) includes a third level die (172). A plurality of first level molding dies (110) may be used. The first level die (110) may be a volatile memory die, the second level dies (142) may be non-volatile memory dies and the third level die (172) may be an active die. In a method of forming the vertical stack system in package, a carrier substrate may be used and later removed.

Abstract translation: 描述了包装结构中的垂直堆叠系统。 包装包括第一级（125）模制件（122）和扇出结构（130），第三级（185）模制件（182）和扇出结构（190）和第二级（155）模制件（152）和 在第一和第三级（125,185）之间的扇出结构（160）。 第一级（125）模制（122）和扇出结构（130）包括第一级模具（110），第二级（155）模制件（152）和扇出结构（160）包括背对背 模具（142），其中每个模具（142）的前表面结合到再分布层（130,160），并且第三级（185）模制件（182）包括第三级模具（172）。 可以使用多个第一级成型模具（110）。 第一级管芯（110）可以是易失性存储器管芯，第二级管芯（142）可以是非易失性存储器管芯，并且第三级管芯（172）可以是有源管芯。 在封装中形成垂直堆叠系统的方法中，可以使用载体衬底并随后去除。

公开(公告)号：WO2020176313A1

公开(公告)日：2020-09-03

申请号：PCT/US2020/018883

申请日：2020-02-19

Applicant: APPLE INC.

Inventor： ZHONG, Chonghua ,  ZHAI, Jun ,  HU, Kunzhong

IPC: H01L23/538

Abstract: Package structure with folded die arrangements and methods of fabrication are described. In an embodiment, a package structure includes a first die and vertical interposer side-by-side. A second die is face down on an electrically connected with the vertical interposer, and a local interposer electrically connects the first die with the vertical interposer.

公开(公告)号：WO2018226394A3

公开(公告)日：2018-12-13

申请号：PCT/US2018/033813

申请日：2018-05-22

Applicant: APPLE INC.

Inventor： ZHAI, Jun ,  ZHONG, Chonghua ,  HU, Kunzhong

IPC: H01L21/60 ,  H01L23/16 ,  H01L23/498 ,  H01L21/48 ,  H01L23/538 ,  H01L25/065 ,  H01L25/10 ,  H01L21/98 ,  H01L21/683 ,  H01L25/18

Abstract: Multiple component package structures are described in which an interposer chiplet (110) is integrated to provide fine routing between components. In an embodiment, the interposer chiplet (110) and a plurality of conductive vias (142) are encapsulated in an encapsulation layer (140). A first plurality of terminals (135A) of the first (130) and second (132) components may be in electrical connection with the plurality of conductive pillars and a second plurality of terminals (135B) of first and second components may be in electrical connection with the interposer chiplet (110).

公开(公告)号：WO2016010859A1

公开(公告)日：2016-01-21

申请号：PCT/US2015/040013

申请日：2015-07-10

Applicant: APPLE INC.

Inventor： ZHAI, Jun ,  HU, Kunzhong ,  ZHONG, Chonghua

IPC: H01L25/10 ,  G11C5/02 ,  H01L25/18

CPC classification number: H01L25/105 ,  H01L23/49811 ,  H01L23/5389 ,  H01L24/19 ,  H01L24/20 ,  H01L25/0657 ,  H01L25/18 ,  H01L25/50 ,  H01L2224/04105 ,  H01L2224/12105 ,  H01L2224/131 ,  H01L2224/16225 ,  H01L2224/16235 ,  H01L2224/32145 ,  H01L2224/32225 ,  H01L2224/73204 ,  H01L2224/73267 ,  H01L2225/1035 ,  H01L2225/1058 ,  H01L2924/15311 ,  H01L2924/18162 ,  H01L2924/014 ,  H01L2924/00

Abstract: In some embodiments, a semiconductor device package on package assembly may include a first package, a second package, and a third package. The first package may include a first surface, a second surface, a first die, and a first set of electrical conductors. The first set of electrical conductors may be configured to electrically connect the package on package assembly. The second package may include a third surface and a fourth surface, and a local memory module. The third surface may be coupled to the second surface. The first package may be electrically coupled to the second package. The third package may include a fifth surface and a sixth surface, and a main memory module. The fifth surface may be coupled to the fourth surface. The third package may be electrically coupled to the first package and/or the second package.

Abstract translation: 在一些实施例中，封装组件上的半导体器件封装可以包括第一封装，第二封装和第三封装。 第一封装可以包括第一表面，第二表面，第一管芯和第一组电导体。 第一组电导体可以被配置为电连接封装组件上的封装。 第二包装可以包括第三表面和第四表面以及本地存储器模块。 第三表面可以联接到第二表面。 第一封装可以电耦合到第二封装。 第三包装可以包括第五表面和第六表面，以及主存储器模块。 第五表面可以联接到第四表面。 第三封装可以电耦合到第一封装和/或第二封装。

公开(公告)号：WO2023019070A1

公开(公告)日：2023-02-16

申请号：PCT/US2022/074392

申请日：2022-08-01

Applicant: APPLE INC.

Inventor： RAMACHANDRAN, Vidhya ,  DABRAL, Sanjay ,  JANGAM, SivaChandra ,  ZHAI, Jun ,  HU, Kunzhong

IPC: H01L23/31 ,  H01L23/522 ,  H01L23/528 ,  H01L23/29 ,  H01L21/56 ,  H01L21/78

Abstract: Chip sealing structures and methods of manufacture are described. In an embodiment, a chip structure includes a main body area formed of a substrate, a back-end-of-the-line (BEOL) build-up structure spanning over the substrate, and chip edge sidewalls extending from a back surface of the substrate to a top surface of the BEOL build-up structure and laterally surrounding the substrate and the BEOL build-up structure. In accordance with embodiments, the chip structure may further include a conformal sealing layer covering at least a first chip edge sidewall of the chip edge sidewalls and a portion of the top surface of the BEOL build-up structure, and forming a lip around the top surface of the BEOL build-up structure.

公开(公告)号：WO2021158419A1

公开(公告)日：2021-08-12

申请号：PCT/US2021/015441

申请日：2021-01-28

Applicant: APPLE INC.

Inventor： DABRAL, Sanjay ,  CAO, Zhitao ,  HU, Kunzhong ,  ZHAI, Jun

IPC: H01L23/50 ,  H01L23/538

Abstract: Electronic package structures and systems are described in which a 3D interconnect structure is integrated into a package redistribution layer and/or chiplet for power and signal delivery to a die. Such structures may significantly improve input output (IO) density and routing quality for signals, while keeping power delivery feasible.

公开(公告)号：WO2020112504A1

公开(公告)日：2020-06-04

申请号：PCT/US2019/062701

申请日：2019-11-21

Applicant: APPLE INC.

Inventor： ZHONG, Chonghua ,  ZHAI, Jun ,  HU, Kunzhong

IPC: H01L25/065 ,  H01L25/10 ,  H01L25/18 ,  H01L23/00

Abstract: Double side mounted package structures and memory modules incorporating such double side mounted package structures are described in which memory packages are mounted on both sides of a module substrate. A routing substrate is mounted to a bottom side of the module substrate to provide general purpose in/out routing and power routing, while signal routing from the logic die to double side mounted memory packages is provided in the module routing. In an embodiment, module substrate is a coreless module substrate and may be thinner than the routing substrate.