公开(公告)号：WO2020242864A1

公开(公告)日：2020-12-03

申请号：PCT/US2020/033857

申请日：2020-05-20

申请人： APPLE INC.

发明人： HSU, Jun Chung ,  CHUNG, Chih-Ming ,  ZHAI, Jun ,  KAO, Yifan ,  JEON, Young Doo ,  KIM, Taegui

IPC分类号： H01L21/48 ,  H01L23/498

摘要： Semiconductor packaging substrates and processing sequences are described. In an embodiment, a packaging substrate includes a build-up structure, and a patterned metal contact layer partially embedded within the build-up structure and protruding from the build-up structure. The patterned metal contact layer may include an array of surface mount (SMT) metal bumps in a chip mount area, a metal dam structure or combination thereof.

公开(公告)号：WO2016140818A2

公开(公告)日：2016-09-09

申请号：PCT/US2016/018801

申请日：2016-02-19

申请人： APPLE INC.

发明人： CHUNG, Chih-Ming ,  ZHAI, Jun ,  YANG, Yizhang

IPC分类号： H01L23/552 ,  H01L23/538 ,  H01L21/60 ,  H01L23/34 ,  H01L25/16

CPC分类号： H01L25/18 ,  H01L21/565 ,  H01L21/568 ,  H01L21/768 ,  H01L23/3107 ,  H01L23/34 ,  H01L23/36 ,  H01L23/3675 ,  H01L23/481 ,  H01L23/49816 ,  H01L23/5383 ,  H01L23/5384 ,  H01L23/5386 ,  H01L23/5389 ,  H01L23/552 ,  H01L24/14 ,  H01L24/19 ,  H01L24/32 ,  H01L24/97 ,  H01L25/0652 ,  H01L25/105 ,  H01L25/16 ,  H01L25/50 ,  H01L2224/0401 ,  H01L2224/04105 ,  H01L2224/12105 ,  H01L2224/13024 ,  H01L2224/131 ,  H01L2224/13144 ,  H01L2224/16227 ,  H01L2224/27318 ,  H01L2224/2732 ,  H01L2224/27436 ,  H01L2224/32145 ,  H01L2224/32225 ,  H01L2224/73204 ,  H01L2224/73253 ,  H01L2224/73267 ,  H01L2224/81005 ,  H01L2224/81203 ,  H01L2224/81815 ,  H01L2224/82031 ,  H01L2224/82039 ,  H01L2224/83005 ,  H01L2224/83191 ,  H01L2224/83855 ,  H01L2224/83862 ,  H01L2224/83874 ,  H01L2224/92225 ,  H01L2224/92244 ,  H01L2224/94 ,  H01L2224/97 ,  H01L2225/06548 ,  H01L2225/06555 ,  H01L2225/06589 ,  H01L2225/1035 ,  H01L2225/1041 ,  H01L2225/1058 ,  H01L2924/12 ,  H01L2924/14 ,  H01L2924/1431 ,  H01L2924/1433 ,  H01L2924/1434 ,  H01L2924/1436 ,  H01L2924/15311 ,  H01L2924/19011 ,  H01L2924/19041 ,  H01L2924/19042 ,  H01L2924/19103 ,  H01L2924/19104 ,  H01L2924/19105 ,  H01L2924/3025 ,  H01L2924/3511 ,  H01L2924/014 ,  H01L2224/27 ,  H01L2224/83 ,  H01L2224/82 ,  H01L2224/81

摘要： Packages and methods of formation are described. In an embodiment, a system in package (SiP) includes first and second redistribution layers (RDLs), stacked die between the first and second RDLs, and conductive pillars extending between the RDLs. A molding compound may encapsulate the stacked die and conductive pillars between the first and second RDLs.

摘要翻译： 描述了包装和形成方法。 在一个实施例中，封装系统（SiP）包括第一和第二再分配层（RDL），第一和第二RDL之间的堆叠管芯，以及在RDL之间延伸的导电柱。 模塑料可以将堆叠的管芯和导电柱塞在第一和第二RDL之间。

公开(公告)号：WO2015031030A1

公开(公告)日：2015-03-05

申请号：PCT/US2014/050312

申请日：2014-08-08

申请人： APPLE INC.

发明人： HSU, Jun, Chung ,  ZHAI, Jun

IPC分类号： H01L23/13 ,  H01L23/498 ,  H01L21/48

CPC分类号： H01L23/13 ,  H01L21/4857 ,  H01L21/76802 ,  H01L23/12 ,  H01L23/481 ,  H01L23/49822 ,  H01L25/0657 ,  H01L25/105 ,  H01L25/50 ,  H01L2224/16225 ,  H01L2224/32225 ,  H01L2224/73204 ,  H01L2225/06513 ,  H01L2225/06517 ,  H01L2225/06548 ,  H01L2225/1023 ,  H01L2225/1058 ,  H01L2924/15153 ,  H01L2924/15311 ,  H01L2924/1533 ,  H01L2924/19106 ,  H01L2924/00

摘要： A bottom package for a PoP (package-on-package) may be formed with a reinforcement layer supporting a thin or coreless substrate. The reinforcement layer may provide stiffness and rigidity to the substrate to increase the stiffness and rigidity of the bottom package and provide better handling of the substrate. The reinforcement layer may be formed using core material, a laminate layer, and a metal layer. The substrate may be formed on the reinforcement layer. The reinforcement layer may include an opening sized to accommodate a die. The die may be coupled to an exposed surface of the substrate in the opening. Metal filled vias through the reinforcement layer may be used to couple the substrate to a top package.

摘要翻译： 用于PoP（封装封装）的底部封装可以形成有支撑薄的或无芯的衬底的加强层。 加强层可以为基底提供刚度和刚度，以增加底部包装的刚度和刚性，并提供更好的基底处理。 加强层可以使用芯材，层压层和金属层形成。 衬底可以形成在加强层上。 加强层可以包括尺寸适于容纳模具的开口。 裸片可以在开口中耦合到衬底的暴露表面。 通过加强层的金属填充的通孔可以用于将衬底耦合到顶部封装。

公开(公告)号：WO2014120484A1

公开(公告)日：2014-08-07

申请号：PCT/US2014/012072

申请日：2014-01-17

申请人： APPLE INC.

发明人： ZHAI, Jun

IPC分类号： H01L25/03 ,  H01L23/00

CPC分类号： H01L23/498 ,  H01L23/3128 ,  H01L23/49816 ,  H01L23/49827 ,  H01L23/49861 ,  H01L23/5386 ,  H01L24/13 ,  H01L24/16 ,  H01L24/29 ,  H01L24/32 ,  H01L24/81 ,  H01L24/83 ,  H01L25/03 ,  H01L2224/131 ,  H01L2224/13124 ,  H01L2224/13147 ,  H01L2224/136 ,  H01L2224/16145 ,  H01L2224/16225 ,  H01L2224/16227 ,  H01L2224/16235 ,  H01L2224/2919 ,  H01L2224/73104 ,  H01L2224/73204 ,  H01L2224/81191 ,  H01L2224/81203 ,  H01L2224/8121 ,  H01L2224/81815 ,  H01L2224/83102 ,  H01L2224/83191 ,  H01L2224/83192 ,  H01L2225/06517 ,  H01L2225/06527 ,  H01L2225/06572 ,  H01L2924/15311 ,  H01L2924/15321 ,  H01L2924/00014 ,  H01L2924/014 ,  H01L2924/0665

摘要： A top package (100) used in a PoP (package-on-package) package includes two memory dies (102A, 102B) stacked with a redistribution layer (RDL) between the die. The first memory die (102A) is encapsulated in an encapsulant (104) and coupled to a top surface of the RDL (106). A second memory die (102B) is coupled to a bottom surface of the RDL. The second memory die is coupled to the RDL with either a capillary underfill material or a non-conductive paste. The RDL includes routing between each of the memory die and one or more terminals (112A, 112B) coupled to the RDL on a periphery of the die.

摘要翻译： 在PoP（封装封装）封装中使用的顶部封装（100）包括在管芯之间堆叠有再分配层（RDL）的两个存储器管芯（102A，102B）。 第一存储器管芯（102A）被封装在密封剂（104）中并且耦合到RDL（106）的顶表面。 第二存储器管芯（102B）耦合到RDL的底表面。 第二个存储器管芯使用毛细管底部填充材料或非导电浆料连接到RDL。 RDL包括在每个存储管芯与在管芯外围连接到RDL的一个或多个端子（112A，112B）之间的布线。

公开(公告)号：WO2023019070A1

公开(公告)日：2023-02-16

申请号：PCT/US2022/074392

申请日：2022-08-01

申请人： APPLE INC.

发明人： RAMACHANDRAN, Vidhya ,  DABRAL, Sanjay ,  JANGAM, SivaChandra ,  ZHAI, Jun ,  HU, Kunzhong

IPC分类号： H01L23/31 ,  H01L23/522 ,  H01L23/528 ,  H01L23/29 ,  H01L21/56 ,  H01L21/78

摘要： Chip sealing structures and methods of manufacture are described. In an embodiment, a chip structure includes a main body area formed of a substrate, a back-end-of-the-line (BEOL) build-up structure spanning over the substrate, and chip edge sidewalls extending from a back surface of the substrate to a top surface of the BEOL build-up structure and laterally surrounding the substrate and the BEOL build-up structure. In accordance with embodiments, the chip structure may further include a conformal sealing layer covering at least a first chip edge sidewall of the chip edge sidewalls and a portion of the top surface of the BEOL build-up structure, and forming a lip around the top surface of the BEOL build-up structure.

公开(公告)号：WO2022108776A1

公开(公告)日：2022-05-27

申请号：PCT/US2021/058397

申请日：2021-11-08

申请人： APPLE INC.

发明人： SHANMUGAM, Karthik ,  CARSON, Flynn P. ,  ZHAI, Jun ,  CAMENFORTE, Raymundo M. ,  LI, Menglu

IPC分类号： H01L23/538 ,  H01L21/683 ,  H01L23/00

摘要： Flexible packages and electronic devices with integrated flexible packages are described. In an embodiment, a flexibly package includes a first die and a second die encapsulated in a molding compound layer. A compliant redistribution layer (RDL) spans the molding compound layer and both dies, and includes electrical routing formed directly on landing pads of the dies. A notch is formed in the molding compound layer between the dies to facilitate flexure of the compliant RDL.

公开(公告)号：WO2021158419A1

公开(公告)日：2021-08-12

申请号：PCT/US2021/015441

申请日：2021-01-28

申请人： APPLE INC.

发明人： DABRAL, Sanjay ,  CAO, Zhitao ,  HU, Kunzhong ,  ZHAI, Jun

IPC分类号： H01L23/50 ,  H01L23/538

摘要： Electronic package structures and systems are described in which a 3D interconnect structure is integrated into a package redistribution layer and/or chiplet for power and signal delivery to a die. Such structures may significantly improve input output (IO) density and routing quality for signals, while keeping power delivery feasible.

公开(公告)号：WO2020112504A1

公开(公告)日：2020-06-04

申请号：PCT/US2019/062701

申请日：2019-11-21

申请人： APPLE INC.

发明人： ZHONG, Chonghua ,  ZHAI, Jun ,  HU, Kunzhong

IPC分类号： H01L25/065 ,  H01L25/10 ,  H01L25/18 ,  H01L23/00

摘要： Double side mounted package structures and memory modules incorporating such double side mounted package structures are described in which memory packages are mounted on both sides of a module substrate. A routing substrate is mounted to a bottom side of the module substrate to provide general purpose in/out routing and power routing, while signal routing from the logic die to double side mounted memory packages is provided in the module routing. In an embodiment, module substrate is a coreless module substrate and may be thinner than the routing substrate.

公开(公告)号：WO2016081182A1

公开(公告)日：2016-05-26

申请号：PCT/US2015/058474

申请日：2015-10-30

申请人： APPLE INC.

发明人： ZHAI, Jun ,  HU, Kunzhong ,  CARSON, Flynn P.

IPC分类号： H01L25/03 ,  H01L21/98 ,  H01L23/31 ,  H01L21/56

CPC分类号： H01L25/0657 ,  H01L21/4853 ,  H01L21/561 ,  H01L21/565 ,  H01L21/568 ,  H01L23/3135 ,  H01L23/49811 ,  H01L23/49838 ,  H01L23/525 ,  H01L23/552 ,  H01L24/19 ,  H01L24/89 ,  H01L24/96 ,  H01L24/97 ,  H01L25/03 ,  H01L25/50 ,  H01L2224/04105 ,  H01L2224/12105 ,  H01L2224/16227 ,  H01L2224/73204 ,  H01L2224/80001 ,  H01L2224/97 ,  H01L2225/0652 ,  H01L2225/06572 ,  H01L2924/15311 ,  H01L2924/18161 ,  H01L2924/18162 ,  H01L2924/19105 ,  H01L2224/81

摘要： Fanout wafer level packages (FOWLPs) and methods of formation are described. In an embodiment, a package includes a first routing layer, a first die on a top side of the first routing layer, and a first molding compound encapsulating the first die on the first routing layer. A first plurality of conductive pillars extends from a bottom side of the first routing layer. A second die is on a top side of a second routing layer, and the first plurality of conductive pillars is on the top side of the second routing layer. A second molding compound encapsulates the first molding compound, the first routing layer, the first plurality of conductive pillars, and the second die on the second routing layer. In an embodiment, a plurality of conductive bumps (e.g. solder balls) extends from a bottom side of the second routing layer.

摘要翻译： 描述了扇出晶片级封装（FOWLP）和形成方法。 在一个实施例中，包装包括第一布线层，第一布线层的顶侧上的第一管芯，以及将第一管芯封装在第一布线层上的第一模制化合物。 第一多个导电柱从第一路由层的底侧延伸。 第二管芯位于第二布线层的顶侧，并且第一多个导电柱位于第二布线层的顶侧。 第二模塑料在第二路由层上封装第一模塑料，第一路由层，第一多个导电柱和第二模。 在一个实施例中，多个导电凸块（例如焊球）从第二布线层的底侧延伸。

公开(公告)号：WO2015020836A3

公开(公告)日：2015-02-12

申请号：PCT/US2014/048603

申请日：2014-07-29

申请人： APPLE INC.

发明人： ZERBE, Jared L. ,  FANG, Emerson S. ,  ZHAI, Jun ,  SEARLES, Shawn

IPC分类号： H01L25/16 ,  H01L23/64 ,  H01G4/228 ,  H01L23/13 ,  H01L25/18 ,  H01L25/065

摘要： A semiconductor device package is described that includes a power consuming device (such as an SOC device). The power consuming device (120) may include one or more current consuming elements. A passive device (100) may be coupled (110) to the power consuming device. The passive device may include a plurality of passive elements formed on a semiconductor substrate. The passive elements may be arranged in an array of structures (102) on the semiconductor substrate. The power consuming device and the passive device may be coupled using one or more terminals (110). The passive device and power consuming device coupling may be configured in such a way that the power consuming device determines functionally the way the passive device elements will be used.