METHODS FOR REDUCING TRANSFER PATTERN DEFECTS IN A SEMICONDUCTOR DEVICE

    公开(公告)号:WO2020185391A1

    公开(公告)日:2020-09-17

    申请号:PCT/US2020/019627

    申请日:2020-02-25

    Abstract: Disclosed are methods for reducing transfer pattern defects in a semiconductor device. In some embodiments, a method includes providing a semiconductor device including a plurality of photoresist lines on a stack of layers, wherein the plurality of photoresist lines includes a bridge defect extending between two or more photoresist lines of the plurality of photoresist lines. The method may further include forming a plurality of mask lines by etching a set of trenches in a first layer of the stack of layers, and removing the bridge defect by etching the bridge defect at a non-zero angle of inclination with respect to a perpendicular to a plane of an upper surface of the stack of layers.

    FULLY SELF-ALIGNED SUBTRACTIVE ETCH
    7.
    发明申请

    公开(公告)号:WO2021252229A1

    公开(公告)日:2021-12-16

    申请号:PCT/US2021/035336

    申请日:2021-06-02

    Abstract: Apparatuses and methods to provide fully self-aligned first metallization lines, M1, via, and second metallization lines, M2, are described. A first metallization line comprises a set of first conductive lines extending along a first direction on a first insulating layer on a substrate; a second metallization line comprising a set of second conductive lines on an etch stop layer above the first metallization line, the set of second conductive lines extending along a second direction that crosses the first direction at an angle; and at least one via between the first metallization line and the second metallization line, the at least one via comprising a via metallization layer, wherein the at least one via is self-aligned along the second direction to one of the first metallization lines and the at least one via is self-aligned along the first direction to one of the second metallization lines, the second direction crossing the first direction at an angle.

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