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公开(公告)号:WO2017023579A1
公开(公告)日:2017-02-09
申请号:PCT/US2016/043624
申请日:2016-07-22
Applicant: INVENSAS CORPORATION
Inventor: UZOH, Cyprian, Emeka , GAO, Guilian , LEE, Bongsub , MCGRATH, Scott , SHEN, Hong , WOYCHIK, Charles, G. , SITARAM, Arkalgud, R. , AGRAWAL, Akash
IPC: H01L23/00 , H01L21/768
CPC classification number: H01L24/03 , H01L21/31144 , H01L21/486 , H01L23/291 , H01L23/293 , H01L23/3171 , H01L23/3192 , H01L23/481 , H01L23/49816 , H01L23/49827 , H01L23/53214 , H01L23/53228 , H01L23/53257 , H01L23/5329 , H01L24/05 , H01L24/11 , H01L24/13 , H01L2224/02126 , H01L2224/03009 , H01L2224/03464 , H01L2224/0401 , H01L2224/05025 , H01L2224/05144 , H01L2224/05155 , H01L2224/0557 , H01L2224/05571 , H01L2224/05572 , H01L2224/0558 , H01L2224/10126 , H01L2224/13016 , H01L2224/13022 , H01L2224/131 , H01L2924/01013 , H01L2924/01028 , H01L2924/01029 , H01L2924/01074 , H01L2924/3511 , H01L2924/00012 , H01L2924/014
Abstract: A method of processing an interconnection element can include providing a substrate element having front and rear opposite surfaces and electrically conductive structure, a first dielectric layer overlying the front surface and a plurality of conductive contacts at a first surface of the first dielectric layer, and a second dielectric layer overlying the rear surface and having a conductive element at a second surface of the second dielectric layer. The method can also include removing a portion of the second dielectric layer so as to reduce the thickness of the portion, and to provide a raised portion of the second dielectric layer having a first thickness and a lowered portion having a second thickness. The first thickness can be greater than the second thickness. At least a portion of the conductive element can be recessed below a height of the first thickness of the second dielectric layer.
Abstract translation: 处理互连元件的方法可以包括提供具有前后相对表面和导电结构的衬底元件,覆盖前表面的第一电介质层和在第一介电层的第一表面处的多个导电触点,以及 第二电介质层覆盖在后表面上并且在第二介电层的第二表面处具有导电元件。 该方法还可以包括去除第二电介质层的一部分以减小该部分的厚度,并且提供具有第一厚度的第二介电层的凸起部分和具有第二厚度的下降部分。 第一厚度可以大于第二厚度。 导电元件的至少一部分可以凹陷到第二介电层的第一厚度的高度以下。
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公开(公告)号:WO2016002455A1
公开(公告)日:2016-01-07
申请号:PCT/JP2015/066781
申请日:2015-06-10
Applicant: JX日鉱日石金属株式会社
IPC: G01T1/24 , H01L27/144 , H01L27/146 , H01L31/08
CPC classification number: G01T1/24 , H01L24/05 , H01L24/06 , H01L24/09 , H01L27/144 , H01L27/146 , H01L27/14634 , H01L27/14636 , H01L27/14676 , H01L27/14696 , H01L31/02005 , H01L31/022408 , H01L31/0296 , H01L31/02966 , H01L31/08 , H01L31/115 , H01L2224/0345 , H01L2224/03464 , H01L2224/0558 , H01L2224/05583 , H01L2224/05584 , H01L2224/05644 , H01L2224/05655 , H01L2224/05664
Abstract: UBM層を形成する時の金属電極層の劣化を抑制し、十分な電気特性を実現する放射線検出器用UBM電極構造体、放射線検出器及びその製造方法を提供する。本発明の放射線検出器用UBM電極構造体は、CdTe又はCdZnTeからなる基板を有する放射線検出器用UBM電極構造体であって、前記基板上に無電解めっきにより形成したPt又はAu電極層と、前記Pt又はAu電極層上にスパッタにより形成したNi層と、前記Ni層上にスパッタにより形成したAu層と、を備える。
Abstract translation: 本发明提供一种放射线检测器UBM电极结构体,放射线检测器及其制造方法,能够抑制UBM层形成时的金属电极层的劣化,能够实现充分的电特性。 根据本发明,辐射检测器UBM电极结构体包括包含CdTe或CdZnTe的衬底,并且通过无电镀形成在衬底上形成的Pt或Au电极层,通过在Pt或Au电极层上形成的Ni层 溅射和通过溅射形成在Ni层上的Au层。
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3.
公开(公告)号:WO2011002778A2
公开(公告)日:2011-01-06
申请号:PCT/US2010040410
申请日:2010-06-29
Applicant: FLIPCHIP INT LLC , BURGESS GUY F , CURTIS ANTHONY , JOHNSON MICHAEL E , STOUT GENE , TESSIER THEODORE G
Inventor: BURGESS GUY F , CURTIS ANTHONY , JOHNSON MICHAEL E , STOUT GENE , TESSIER THEODORE G
IPC: H01L21/60 , H01L23/488
CPC classification number: H01L24/11 , H01L21/563 , H01L24/03 , H01L24/13 , H01L24/14 , H01L24/16 , H01L24/81 , H01L2224/0345 , H01L2224/03464 , H01L2224/0361 , H01L2224/03912 , H01L2224/0401 , H01L2224/1132 , H01L2224/11462 , H01L2224/1147 , H01L2224/11472 , H01L2224/11474 , H01L2224/11505 , H01L2224/1184 , H01L2224/11849 , H01L2224/119 , H01L2224/11901 , H01L2224/11903 , H01L2224/13012 , H01L2224/13013 , H01L2224/13014 , H01L2224/13024 , H01L2224/13082 , H01L2224/13083 , H01L2224/13101 , H01L2224/13111 , H01L2224/13116 , H01L2224/13117 , H01L2224/13118 , H01L2224/13124 , H01L2224/13139 , H01L2224/13144 , H01L2224/13147 , H01L2224/13155 , H01L2224/13164 , H01L2224/13294 , H01L2224/133 , H01L2224/13339 , H01L2224/1403 , H01L2224/16225 , H01L2224/16227 , H01L2224/73204 , H01L2224/81191 , H01L2224/81815 , H01L2224/8184 , H01L2224/831 , H01L2924/01013 , H01L2924/01029 , H01L2924/01033 , H01L2924/01046 , H01L2924/01047 , H01L2924/01049 , H01L2924/01051 , H01L2924/01075 , H01L2924/01078 , H01L2924/01079 , H01L2924/01082 , H01L2924/01327 , H01L2924/014 , H01L2924/381 , H01L2924/01028 , H01L2924/0105 , H01L2924/01048 , H01L2924/01032 , H01L2924/00014 , H01L2924/00012
Abstract: In wafer-level chip-scale packaging and flip-chip packaging and assemblies, a solder cap is formed on a vertical pillar. In one embodiment, the vertical pillar overlies a semiconductor substrate. A solder paste, which may be doped with at least one trace element, is applied on a top surface of the pillar structure. A reflow process is performed after applying the solder paste to provide the solder cap.
Abstract translation: 在晶片级芯片级封装和倒装芯片封装和组装中,在垂直柱上形成焊锡帽。 在一个实施例中,垂直柱覆盖半导体衬底。 可以在柱结构的顶表面上施加可以掺杂有至少一个微量元素的焊膏。 在施加焊膏以提供焊锡帽之后进行回流工艺。
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4.INTEGRATED CIRCUIT CHIP USING TOP POST-PASSIVATION TECHNOLOGY AND BOTTOM STRUCTURE TECHNOLOGY 审中-公开
Title translation: 使用顶尖后置技术和底部结构技术的集成电路芯片公开(公告)号:WO2010114687A1
公开(公告)日:2010-10-07
申请号:PCT/US2010/027056
申请日:2010-03-11
Applicant: MEGICA CORPORATION , LIN, Mou-Shiung , LEE, Jin-Yuan , LO, Hsin-Jung , YANG, Ping-Jung , LIU, Te-Sheng
Inventor: LIN, Mou-Shiung , LEE, Jin-Yuan , LO, Hsin-Jung , YANG, Ping-Jung , LIU, Te-Sheng
CPC classification number: G06F1/16 , G11C5/147 , H01L21/563 , H01L23/3128 , H01L23/3171 , H01L23/3192 , H01L23/481 , H01L23/5223 , H01L23/5227 , H01L23/60 , H01L23/66 , H01L24/02 , H01L24/03 , H01L24/05 , H01L24/06 , H01L24/11 , H01L24/13 , H01L24/14 , H01L24/16 , H01L24/17 , H01L24/29 , H01L24/32 , H01L24/33 , H01L24/45 , H01L24/48 , H01L24/49 , H01L24/50 , H01L24/73 , H01L24/81 , H01L24/83 , H01L24/85 , H01L24/92 , H01L24/94 , H01L24/97 , H01L25/0657 , H01L25/16 , H01L25/18 , H01L25/50 , H01L2223/6611 , H01L2223/6666 , H01L2224/02166 , H01L2224/02311 , H01L2224/02313 , H01L2224/02321 , H01L2224/0233 , H01L2224/02331 , H01L2224/0235 , H01L2224/0237 , H01L2224/02371 , H01L2224/02375 , H01L2224/02381 , H01L2224/0239 , H01L2224/024 , H01L2224/0345 , H01L2224/03462 , H01L2224/03464 , H01L2224/03612 , H01L2224/03614 , H01L2224/03912 , H01L2224/0392 , H01L2224/0401 , H01L2224/04042 , H01L2224/05024 , H01L2224/05027 , H01L2224/05155 , H01L2224/05166 , H01L2224/05171 , H01L2224/05176 , H01L2224/05181 , H01L2224/05187 , H01L2224/05541 , H01L2224/05548 , H01L2224/05554 , H01L2224/0556 , H01L2224/05567 , H01L2224/05572 , H01L2224/056 , H01L2224/05624 , H01L2224/05639 , H01L2224/05644 , H01L2224/05647 , H01L2224/05655 , H01L2224/05664 , H01L2224/05669 , H01L2224/05673 , H01L2224/05676 , H01L2224/11 , H01L2224/11009 , H01L2224/1132 , H01L2224/11334 , H01L2224/11462 , H01L2224/11464 , H01L2224/1147 , H01L2224/11849 , H01L2224/119 , H01L2224/1191 , H01L2224/13 , H01L2224/13006 , H01L2224/1302 , H01L2224/13022 , H01L2224/13024 , H01L2224/13082 , H01L2224/13083 , H01L2224/13084 , H01L2224/13099 , H01L2224/131 , H01L2224/13109 , H01L2224/13111 , H01L2224/13113 , H01L2224/13124 , H01L2224/13139 , H01L2224/13144 , H01L2224/13147 , H01L2224/13155 , H01L2224/13164 , H01L2224/13169 , H01L2224/13294 , H01L2224/133 , H01L2224/13311 , H01L2224/13609 , H01L2224/1403 , H01L2224/1411 , H01L2224/14181 , H01L2224/16145 , H01L2224/16225 , H01L2224/16227 , H01L2224/16245 , H01L2224/16265 , H01L2224/17181 , H01L2224/2919 , H01L2224/2929 , H01L2224/29294 , H01L2224/293 , H01L2224/29339 , H01L2224/32105 , H01L2224/32145 , H01L2224/32225 , H01L2224/32245 , H01L2224/33181 , H01L2224/45124 , H01L2224/45144 , H01L2224/45147 , H01L2224/48091 , H01L2224/48111 , H01L2224/48145 , H01L2224/48227 , H01L2224/48247 , H01L2224/48465 , H01L2224/48624 , H01L2224/48644 , H01L2224/48647 , H01L2224/48664 , H01L2224/48669 , H01L2224/48764 , H01L2224/48769 , H01L2224/48824 , H01L2224/48844 , H01L2224/48847 , H01L2224/48864 , H01L2224/4911 , H01L2224/49175 , H01L2224/4918 , H01L2224/73203 , H01L2224/73204 , H01L2224/73207 , H01L2224/73215 , H01L2224/73253 , H01L2224/73257 , H01L2224/73265 , H01L2224/81191 , H01L2224/81411 , H01L2224/81444 , H01L2224/81801 , H01L2224/81815 , H01L2224/8185 , H01L2224/81895 , H01L2224/81903 , H01L2224/83101 , H01L2224/83104 , H01L2224/83851 , H01L2224/92 , H01L2224/9202 , H01L2224/92125 , H01L2224/92127 , H01L2224/92147 , H01L2224/92225 , H01L2224/92247 , H01L2224/94 , H01L2224/97 , H01L2225/06506 , H01L2225/0651 , H01L2225/06513 , H01L2225/06517 , H01L2225/06541 , H01L2225/06562 , H01L2225/06589 , H01L2225/1023 , H01L2225/1029 , H01L2225/1058 , H01L2225/107 , H01L2924/01005 , H01L2924/01006 , H01L2924/01007 , H01L2924/01011 , H01L2924/01013 , H01L2924/01014 , H01L2924/01015 , H01L2924/01018 , H01L2924/01019 , H01L2924/0102 , H01L2924/01022 , H01L2924/01023 , H01L2924/01024 , H01L2924/01027 , H01L2924/01028 , H01L2924/01029 , H01L2924/01031 , H01L2924/01032 , H01L2924/01033 , H01L2924/01041 , H01L2924/01042 , H01L2924/01044 , H01L2924/01045 , H01L2924/01046 , H01L2924/01047 , H01L2924/01049 , H01L2924/0105 , H01L2924/01051 , H01L2924/01056 , H01L2924/01059 , H01L2924/01068 , H01L2924/01072 , H01L2924/01073 , H01L2924/01074 , H01L2924/01075 , H01L2924/01077 , H01L2924/01078 , H01L2924/01079 , H01L2924/01082 , H01L2924/01083 , H01L2924/01322 , H01L2924/01327 , H01L2924/014 , H01L2924/04941 , H01L2924/04953 , H01L2924/05042 , H01L2924/09701 , H01L2924/10253 , H01L2924/10329 , H01L2924/12041 , H01L2924/12042 , H01L2924/1305 , H01L2924/13091 , H01L2924/14 , H01L2924/1421 , H01L2924/1433 , H01L2924/15311 , H01L2924/15787 , H01L2924/15788 , H01L2924/181 , H01L2924/19041 , H01L2924/19042 , H01L2924/19043 , H01L2924/19104 , H01L2924/19105 , H01L2924/30105 , H01L2924/3025 , H01L2924/00014 , H01L2924/00 , H01L2224/48869 , H01L2224/48744 , H01L2924/00012 , H01L2224/03 , H01L2224/0361 , H01L2924/0665 , H01L2224/81 , H01L2224/83 , H01L24/78 , H01L2224/85 , H01L21/56 , H01L21/78 , H01L2924/0635 , H01L2924/07025 , H01L21/304 , H01L21/76898 , H01L2224/0231
Abstract: Integrated circuit chips and chip packages are disclosed that include an over-passivation scheme at a top of the integrated circuit chip and a bottom scheme at a bottom of the integrated circuit chip using a top post-passivation technology and a bottom structure technology. The integrated circuit chips can be connected to an external circuit or structure, such as ball-grid-array (BGA) substrate, printed circuit board, semiconductor chip, metal substrate, glass substrate or ceramic substrate, through the over-passivation scheme or the bottom scheme. Related fabrication techniques are described.
Abstract translation: 公开了集成电路芯片和芯片封装,其包括在集成电路芯片的顶部处的过钝化方案,以及使用顶部后钝化技术和底部结构技术的集成电路芯片的底部的底部方案。 集成电路芯片可以通过过钝化方案或者通过钝化方案连接到外部电路或结构,例如球栅阵列(BGA)衬底,印刷电路板,半导体芯片,金属衬底,玻璃衬底或陶瓷衬底 底部方案。 描述了相关的制造技术。
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公开(公告)号:WO2007138922A1
公开(公告)日:2007-12-06
申请号:PCT/JP2007/060423
申请日:2007-05-22
Applicant: 日本電気株式会社 , NECエレクトロニクス株式会社 , 曽川 禎道 , 山崎 隆雄 , 高橋 信明
IPC: H01L21/60 , H01L21/3205 , H01L23/52
CPC classification number: H01L23/49866 , H01L21/563 , H01L23/24 , H01L23/3128 , H01L23/49816 , H01L24/03 , H01L24/05 , H01L24/11 , H01L24/13 , H01L24/16 , H01L24/75 , H01L24/81 , H01L2224/0345 , H01L2224/03462 , H01L2224/03464 , H01L2224/0362 , H01L2224/03828 , H01L2224/0401 , H01L2224/05073 , H01L2224/05082 , H01L2224/05083 , H01L2224/05084 , H01L2224/05118 , H01L2224/05147 , H01L2224/05155 , H01L2224/05157 , H01L2224/0516 , H01L2224/05164 , H01L2224/05166 , H01L2224/05169 , H01L2224/05171 , H01L2224/05571 , H01L2224/05647 , H01L2224/05655 , H01L2224/1132 , H01L2224/1145 , H01L2224/11462 , H01L2224/1147 , H01L2224/115 , H01L2224/11502 , H01L2224/1152 , H01L2224/11849 , H01L2224/13006 , H01L2224/13022 , H01L2224/13111 , H01L2224/16225 , H01L2224/32225 , H01L2224/73204 , H01L2224/75702 , H01L2224/8121 , H01L2224/81447 , H01L2224/81455 , H01L2224/81815 , H01L2224/83104 , H01L2924/00014 , H01L2924/0002 , H01L2924/01005 , H01L2924/01006 , H01L2924/01007 , H01L2924/01011 , H01L2924/01013 , H01L2924/01015 , H01L2924/01022 , H01L2924/01024 , H01L2924/01027 , H01L2924/01028 , H01L2924/01029 , H01L2924/0103 , H01L2924/01033 , H01L2924/01046 , H01L2924/01047 , H01L2924/0105 , H01L2924/01074 , H01L2924/01078 , H01L2924/01079 , H01L2924/01082 , H01L2924/01327 , H01L2924/014 , H01L2924/09701 , H01L2924/15311 , H01L2924/15787 , H01L2924/181 , H01L2924/19041 , H01L2924/19043 , H01L2924/3512 , H01L2924/3651 , H05K3/244 , H05K3/3436 , H05K3/3463 , H01L2924/00 , H01L2224/05552 , H01L2924/00012
Abstract: 従来のCuやNi、NiPなどのUBMでは電子部品を長期間、高温状態で保持することにより、UBMのバリア性が破壊されたり、接合界面に脆弱な合金層が形成されるために接合強度が低下するという問題があった。本発明ではこのような高温保管後にハンダ接合部の長期接続信頼性が低下する問題を改善する。 基板上又は半導体素子上に設けられた電極パッドと、電極パッドを覆うように設けられたバリアメタル層とを有し、バリアメタル層は、電極パッドに接する側と反対側に15~60at%のCu及び40~85at%のNiを含むCuNi系合層を有することを特徴とする電子部品。
Abstract translation: 在诸如Cu,Ni和NiP的常规UBM中存在由于长期在高温状态下保持电子元件而使UBM的阻挡特性被破坏的问题,并且由于 以在接合界面上形成脆性合金层。 提高了高温保存后焊接部的长期连接可靠性恶化的问题。 电子部件设置有布置在基板或半导体元件上的电极焊盘和布置成覆盖电极焊盘的阻挡金属层。 阻挡金属层具有在与电极焊盘接触的一侧相反一侧的CuNi合金层,其包含15-60at%的Cu和40-85at%的Ni。
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6.METHOD OF CONNECTING A CONNECTING WIRE TO A CONTACT OF AN INTEGRATED CIRCUIT 审中-公开
Title translation: 方法用于连接连接线与连接接触AN集成电路公开(公告)号:WO00057472A1
公开(公告)日:2000-09-28
申请号:PCT/DE2000/000907
申请日:2000-03-24
IPC: H01L21/603 , H01L23/485
CPC classification number: H01L24/85 , H01L24/03 , H01L24/05 , H01L24/45 , H01L24/48 , H01L24/78 , H01L2224/02166 , H01L2224/03422 , H01L2224/03436 , H01L2224/03464 , H01L2224/04042 , H01L2224/05073 , H01L2224/05147 , H01L2224/05601 , H01L2224/05609 , H01L2224/05611 , H01L2224/05616 , H01L2224/05624 , H01L2224/05647 , H01L2224/05666 , H01L2224/32225 , H01L2224/45014 , H01L2224/45015 , H01L2224/45032 , H01L2224/45124 , H01L2224/45139 , H01L2224/45144 , H01L2224/45147 , H01L2224/45155 , H01L2224/4556 , H01L2224/45565 , H01L2224/456 , H01L2224/45686 , H01L2224/48091 , H01L2224/48247 , H01L2224/48463 , H01L2224/4847 , H01L2224/48601 , H01L2224/48609 , H01L2224/48611 , H01L2224/48616 , H01L2224/48624 , H01L2224/48647 , H01L2224/48666 , H01L2224/48701 , H01L2224/48709 , H01L2224/48711 , H01L2224/48716 , H01L2224/48724 , H01L2224/48747 , H01L2224/48766 , H01L2224/48801 , H01L2224/48809 , H01L2224/48811 , H01L2224/48816 , H01L2224/48847 , H01L2224/48866 , H01L2224/78252 , H01L2224/78313 , H01L2224/85075 , H01L2224/85201 , H01L2224/8581 , H01L2224/85815 , H01L2224/85825 , H01L2224/8583 , H01L2924/00011 , H01L2924/01005 , H01L2924/01006 , H01L2924/01007 , H01L2924/01013 , H01L2924/01018 , H01L2924/0102 , H01L2924/01022 , H01L2924/01028 , H01L2924/01029 , H01L2924/01031 , H01L2924/01033 , H01L2924/01047 , H01L2924/01049 , H01L2924/0105 , H01L2924/01052 , H01L2924/01061 , H01L2924/01068 , H01L2924/01079 , H01L2924/01082 , H01L2924/01322 , H01L2924/01327 , H01L2924/014 , H01L2924/04941 , H01L2924/14 , H01L2924/00014 , H01L2224/45666 , H01L2224/45647 , H01L2924/0494 , H01L2924/01014 , H01L2924/00015 , H01L2924/0108 , H01L2224/45611 , H01L2924/00 , H01L2224/48824
Abstract: An integrated circuit (1) with a semiconductor substrate (2) comprises electrically active zones to which an electric voltage can be applied via contacts (3). The contacts (3) comprise a contact layer made of copper. The invention provides for each contact (3) to present a connecting wire (7), as well as for a solder layer (6) consisting substantially of a solder-metal compound to be located in an area between the connecting wire (7) and the contact (3).
Abstract translation: 一种集成电路(1),包括一个半导体衬底(2)具有通过连接触点(3)与电电压作用时电有源区。 连接接点(3)具有由铜构成的连接层,其中,在每个连接接触件(3)设有一个连接线(7),且进一步其中在所述连接线(7)和终端之间的区域(3)提供了一种钎焊层(6), 基本上由焊料金属化合物。
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7.SEMICONDUCTOR DEVICE PROCESSING METHOD FOR MATERIAL REMOVAL 审中-公开
Title translation: 用于材料去除的半导体器件处理方法公开(公告)号:WO2017007988A1
公开(公告)日:2017-01-12
申请号:PCT/US2016/041443
申请日:2016-07-08
Applicant: DECA TECHNOLOGIES INC.
Inventor: OLSON, Timothy, L. , ROGERS, William, Boyd , ALDAS, Ferdinand
IPC: H01L21/308
CPC classification number: H01L21/30604 , H01L21/568 , H01L21/67784 , H01L24/03 , H01L24/05 , H01L24/19 , H01L24/75 , H01L24/76 , H01L24/96 , H01L2224/0345 , H01L2224/03452 , H01L2224/03462 , H01L2224/03464 , H01L2224/03614 , H01L2224/0381 , H01L2224/0391 , H01L2224/0401 , H01L2224/04105 , H01L2224/05111 , H01L2224/05124 , H01L2224/05139 , H01L2224/05144 , H01L2224/05147 , H01L2224/05155 , H01L2224/742 , H01L2224/7501 , H01L2224/75651 , H01L2224/7665 , H01L2224/94 , H01L2924/18162 , H01L2224/214
Abstract: A method of removing at least a portion of a layer of material from over a semiconductor substrate that can include dispensing an etching solution over the semiconductor substrate to form a pool of etching solution on the layer of material, wherein a footprint of the pool of etching solution is less than a footprint of the semiconductor substrate. The pool of etching solution and the semiconductor substrate can be moved with respect to each other. A pool boundary of the pool of etching solution can be defined on the semiconductor substrate with at least one air-knife such that the pool of etching solution etches the layer of material over the semiconductor substrate within the footprint of the pool of etching solution. The etching solution and at least a portion of the layer of material etched by the etching solution can be removed with the at least one air-knife.
Abstract translation: 一种从半导体衬底上去除材料层的至少一部分的方法,其可以包括在半导体衬底上分配蚀刻溶液以在该材料层上形成蚀刻溶液池,其中蚀刻池的覆盖区 溶液小于半导体衬底的覆盖区。 蚀刻溶液池和半导体衬底可以相对于彼此移动。 可以使用至少一个气刀在半导体衬底上限定蚀刻溶液池的池边界,使得蚀刻溶液池在蚀刻溶液池的覆盖区内蚀刻半导体衬底上的材料层。 蚀刻溶液和由蚀刻溶液蚀刻的材料层的至少一部分可以用至少一个气刀去除。
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8.
公开(公告)号:WO2016157589A1
公开(公告)日:2016-10-06
申请号:PCT/JP2015/080595
申请日:2015-10-29
Applicant: JX金属株式会社
IPC: H01L31/00 , G01T1/24 , H01L27/144 , H01L27/146 , H01L31/08 , H01L31/10
CPC classification number: H01L24/05 , G01T1/24 , G01T1/241 , H01L24/03 , H01L27/144 , H01L27/146 , H01L27/14634 , H01L27/14636 , H01L27/14659 , H01L27/14661 , H01L27/1469 , H01L27/14696 , H01L31/00 , H01L31/08 , H01L31/10 , H01L2224/03464 , H01L2224/0401 , H01L2224/05083 , H01L2224/05144 , H01L2224/05155 , H01L2224/05169 , H01L2924/10373 , H01L2924/10378 , H01L2924/12043 , H01L2924/1433
Abstract: 電極の密着性が高く、剥離を抑制する放射線検出器用UBM電極構造体、それを備えた放射線検出器を提供する。また、UBM構造形成、半田接合工程、又はPt層への信号線の接合時に剥離が生じない放射線検出器用UBM電極構造体の製造方法及びそれを用いた放射線検出器の製造方法を提供する。本発明の放射線検出器用UBM電極構造体は、CdTe基板又はCdZnTe基板と、前記CdTe基板又は前記CdZnTe基板に配置したPt電極層とを備え、前記CdTe基板又は前記CdZnTe基板に対する前記Pt電極層の密着性が0.5N/cm以上である。
Abstract translation: 提供一种用于具有高电极粘合强度和最小剥离的辐射检测器的UBM电极结构,以及具有用于辐射检测器的UBM电极结构的辐射检测器。 还提供了一种制造用于辐射检测器的UBM电极结构的方法,其中在UBM结构形成期间,在焊接步骤期间或在将信号线接合到Pt层期间不发生剥离; 以及其中使用用于制造用于放射线检测器的UBM电极结构的方法的辐射检测器的制造方法。 用于放射线检测器的UBM电极结构设置有CdTe衬底或CdZnTe衬底,以及设置在CdTe衬底或CdZnTe衬底上的Pt电极层。 Pt电极层在CdTe衬底或CdZnTe衬底上的粘合强度至少为0.5N / cm。
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9.IC DIE, ULTRASOUND PROBE, ULTRASONIC DIAGNOSTIC SYSTEM AND METHOD 审中-公开
Title translation: IC DIE,超声探头,超声诊断系统及方法公开(公告)号:WO2015150385A2
公开(公告)日:2015-10-08
申请号:PCT/EP2015/057030
申请日:2015-03-31
Applicant: KONINKLIJKE PHILIPS N.V.
Inventor: JACOBS, Egbertus Reinier , WEEKAMP, Johannes Wilhelmus , RIJKERS, Niels Cornelis Wilhelmus Johannes
CPC classification number: B06B1/0292 , A61B8/12 , A61B8/445 , A61B8/4494 , H01L21/78 , H01L24/01 , H01L24/03 , H01L24/06 , H01L41/0475 , H01L2224/0345 , H01L2224/03462 , H01L2224/03464 , H01L2224/0362 , H01L2224/05005 , H01L2224/05147 , H01L2224/05155 , H01L2224/05166 , H01L2224/05171 , H01L2924/1433 , H01L2924/2064 , H01L2924/20641 , H02N1/006 , H05K1/181 , H05K2201/10151
Abstract: An integrated circuit (IC) die (100) is disclosed having a major surface delimited by at least one edge (102) of the IC die, said major surface carrying a plurality of electrically conductive contact plates (130) extending from said major surface beyond the at least one edge such that each contact plate includes an exposed contact surface portion (132) delimited by the at least one edge for mating with an electrically conductive further contact surface portion (230) on at least one further edge (220) of a body (200), said at least one further edge delimiting a cavity for receiving the IC die. An ultrasound probe including such an IC die and a method of providing such an IC die with contacts are also disclosed.
Abstract translation: 公开了一种集成电路(IC)管芯(100),其具有由IC管芯的至少一个边缘(102)限定的主表面,所述主表面承载从所述主表面延伸超过的多个导电接触板(130) 所述至少一个边缘使得每个接触板包括由所述至少一个边缘限定的暴露的接触表面部分(132),用于在至少一个另外的边缘(220)上与导电的另外的接触表面部分(230)配合 所述至少一个另外的边缘限定用于容纳IC管芯的空腔。 还公开了一种包括这种IC芯片的超声波探头以及提供具有触点的IC芯片的方法。
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公开(公告)号:WO2015033652A1
公开(公告)日:2015-03-12
申请号:PCT/JP2014/067551
申请日:2014-07-01
Applicant: オリンパス株式会社
IPC: H01L21/3205 , H01L21/60 , H01L21/768 , H01L23/522
CPC classification number: H01L24/05 , H01L22/14 , H01L24/03 , H01L24/13 , H01L24/94 , H01L2224/03001 , H01L2224/03464 , H01L2224/0347 , H01L2224/0401 , H01L2224/05009 , H01L2224/05644 , H01L2224/05647 , H01L2224/05655 , H01L2224/13026 , H01L2224/94 , H01L2924/00014 , H01L2224/03 , H01L2924/00012
Abstract: この半導体基板の製造方法は、基板部に複数の素子領域を形成する素子形成工程と、前記素子領域と接続された回路配線を形成する第一配線工程と、複数の電極パッドを形成する電極パッド形成工程と、複数の前記電極パッドの少なくとも一部を電気的に接続する電位調節配線を形成する第二配線工程と、前記第二配線工程後に、無電解めっきにより前記電極パッド上に電極本体を形成する電極形成工程と、前記電極形成工程後に、前記電位調節配線による接続を解除する電位調節解除工程と、を備える。
Abstract translation: 该半导体基板的制造方法具备:在基板部形成多个元件区域的元件形成工序; 用于形成连接到元件区域的电路布线的第一布线步骤; 用于形成多个电极焊盘的电极焊盘形成步骤; 第二布线步骤,用于形成电连接所述多个电极焊盘中的至少一些的电位调节布线; 电极形成步骤,用于在所述第二布线步骤之后通过无电解电镀在所述电极焊盘上形成电极体; 以及用于在电极形成步骤之后通过电位调节布线终止连接的电位调整终止步骤。
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