公开(公告)号：WO2015128399A2

公开(公告)日：2015-09-03

申请号：PCT/EP2015053984

申请日：2015-02-26

Applicant: COMMISSARIAT L ÉNERGIE ATOMIQUE ET AUX ÉNERGIES ALTERNATIVES

Inventor： GONDCHARTON PAUL ,  BENAISSA LAMINE ,  IMBERT BRUNO ,  MORICEAU HUBERT

IPC: H01L21/60 ,  H01L21/768 ,  H01L21/98 ,  H01L23/485

CPC classification number: H01L24/83 ,  H01L21/185 ,  H01L24/03 ,  H01L24/05 ,  H01L24/27 ,  H01L24/29 ,  H01L24/80 ,  H01L25/0657 ,  H01L25/50 ,  H01L2224/0345 ,  H01L2224/03452 ,  H01L2224/0381 ,  H01L2224/03845 ,  H01L2224/05073 ,  H01L2224/0508 ,  H01L2224/05147 ,  H01L2224/05166 ,  H01L2224/05181 ,  H01L2224/05184 ,  H01L2224/05186 ,  H01L2224/05571 ,  H01L2224/05647 ,  H01L2224/2745 ,  H01L2224/2755 ,  H01L2224/27845 ,  H01L2224/29147 ,  H01L2224/80055 ,  H01L2224/80357 ,  H01L2224/8083 ,  H01L2224/80895 ,  H01L2224/80896 ,  H01L2224/8092 ,  H01L2224/80948 ,  H01L2224/83895 ,  H01L2225/06524 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01008 ,  H01L2924/01015 ,  H01L2924/01016 ,  H01L2924/01017 ,  H01L2924/04941 ,  H01L2924/04953 ,  H01L2924/00014 ,  H01L2924/049 ,  H01L2924/00012

Abstract: Process for producing a structure by direct adhesive bonding of two elements comprising the production of the elements to be assembled and the assembly of said elements, in which the production of the elements to be assembled comprises the steps: - deposition on a substrate of a TiN layer by physical vapour deposition, - deposition of a copper layer on the TiN layer, and in which the assembly of said elements comprises the steps: - polishing the surfaces of the copper layers intended to come into contact so that they have a roughness of less than 1 nm RMS and hydrophilic properties, - bringing said surfaces into contact, - storing said structure at atmospheric pressure and at ambient temperature.

Abstract translation: 用于通过直接粘合两种元件来生产结构的方法，包括要组装的元件的生产和所述元件的组装，其中要组装的元件的生产包括以下步骤： - 沉积在TiN的基底上 层，通过物理气相沉积， - 在TiN层上沉积铜层，并且其中所述元件的组件包括以下步骤： - 抛光用于接触的铜层的表面，使得它们具有较小的粗糙度 超过1nm的RMS和亲水性， - 使所述表面接触， - 在大气压和环境温度下储存所述结构。

公开(公告)号：WO2013138006A1

公开(公告)日：2013-09-19

申请号：PCT/US2013/025758

申请日：2013-02-12

Applicant: MICRON TECHNOLOGY, INC.

Inventor： GANDHI, Jaspreet, S.

IPC: H01L21/28 ,  H01L21/304

CPC classification number: H01L24/14 ,  H01L21/6835 ,  H01L21/7684 ,  H01L21/76898 ,  H01L23/3171 ,  H01L23/3192 ,  H01L24/03 ,  H01L24/05 ,  H01L24/11 ,  H01L24/13 ,  H01L2221/68327 ,  H01L2221/6834 ,  H01L2224/03462 ,  H01L2224/0347 ,  H01L2224/0361 ,  H01L2224/03825 ,  H01L2224/0384 ,  H01L2224/03845 ,  H01L2224/03914 ,  H01L2224/0401 ,  H01L2224/05009 ,  H01L2224/05016 ,  H01L2224/05018 ,  H01L2224/05019 ,  H01L2224/05022 ,  H01L2224/05023 ,  H01L2224/05025 ,  H01L2224/0508 ,  H01L2224/05147 ,  H01L2224/05155 ,  H01L2224/05166 ,  H01L2224/05555 ,  H01L2224/05556 ,  H01L2224/05564 ,  H01L2224/05568 ,  H01L2224/05655 ,  H01L2224/05664 ,  H01L2224/11622 ,  H01L2224/1182 ,  H01L2224/1184 ,  H01L2224/13023 ,  H01L2224/131 ,  H01L2224/13147 ,  H01L2924/00014 ,  H01L2924/01022 ,  H01L2924/01028 ,  H01L2924/01044 ,  H01L2924/01046 ,  H01L2924/05042 ,  H01L2924/0538 ,  H01L2924/05442 ,  H01L2924/07025 ,  H01L2924/10253 ,  H01L2924/01029 ,  H01L2924/014 ,  H01L2924/00012 ,  H01L2224/05552

Abstract: Some embodiments include a planarization method. A liner is formed across a semiconductor substrate and along posts that extending upwardly from the substrate. Organic fill material is formed over the liner and between the posts. A planarized surface is formed which extends across the posts and across one or both of the liner and the fill material. Some embodiments include a semiconductor construction containing a semiconductor die. Electrically conductive posts extend through the die. The posts have upper surfaces above a backside surface of the die, and have sidewall surfaces extending between the backside surface and the upper surfaces. A liner is across the backside surface of the die and along the sidewall surfaces of the posts. Electrically conductive caps are over the upper surfaces of the posts, and have rims along the liner adjacent the sidewall surfaces of the posts.

Abstract translation: 一些实施例包括平面化方法。 衬套跨越半导体衬底并沿着从衬底向上延伸的柱形成。 有机填充材料形成在衬里上和柱之间。 形成平面化的表面，该平面化表面延伸穿过柱并穿过衬套和填充材料中的一个或两个。 一些实施例包括包含半导体管芯的半导体结构。 导电柱延伸穿过模具。 柱具有在模具的背面上方的上表面，并且具有在背面和上表面之间延伸的侧壁表面。 衬套穿过模具的后表面并且沿着柱的侧壁表面。 导电盖在柱的上表面之上，并且沿着邻近柱的侧壁表面的衬垫具有边缘。

公开(公告)号：WO2013073440A1

公开(公告)日：2013-05-23

申请号：PCT/JP2012/078935

申请日：2012-11-08

Applicant: 田中貴金属工業株式会社

Inventor： 小柏　俊典 ,  栗田　昌昭 ,  西森　尚 ,  兼平　幸男

IPC: H01L21/60 ,  H01L23/12 ,  H05K1/09 ,  H05K3/20

CPC classification number: H01L21/4814 ,  B22F7/08 ,  B23K35/007 ,  B23K35/0244 ,  B23K35/025 ,  B23K35/3006 ,  B23K35/3013 ,  B23K35/322 ,  B23K2035/008 ,  B23K2201/40 ,  B32B15/018 ,  C22C5/02 ,  C22C5/04 ,  C23C18/165 ,  C25D7/00 ,  H01L21/71 ,  H01L24/03 ,  H01L24/05 ,  H01L24/11 ,  H01L24/13 ,  H01L24/94 ,  H01L2224/03003 ,  H01L2224/031 ,  H01L2224/0312 ,  H01L2224/03334 ,  H01L2224/0401 ,  H01L2224/0508 ,  H01L2224/05082 ,  H01L2224/05083 ,  H01L2224/05139 ,  H01L2224/05144 ,  H01L2224/05166 ,  H01L2224/05169 ,  H01L2224/05639 ,  H01L2224/05644 ,  H01L2224/05647 ,  H01L2224/05655 ,  H01L2224/05664 ,  H01L2224/05666 ,  H01L2224/05669 ,  H01L2224/0567 ,  H01L2224/05671 ,  H01L2224/05673 ,  H01L2224/05676 ,  H01L2224/05678 ,  H01L2224/05681 ,  H01L2224/05684 ,  H01L2224/11003 ,  H01L2224/111 ,  H01L2224/1112 ,  H01L2224/11334 ,  H01L2224/11505 ,  H01L2224/13082 ,  H01L2224/13083 ,  H01L2224/13139 ,  H01L2224/13144 ,  H01L2224/13147 ,  H01L2224/13155 ,  H01L2224/13164 ,  H01L2224/13166 ,  H01L2224/13169 ,  H01L2224/1317 ,  H01L2224/13171 ,  H01L2224/13173 ,  H01L2224/13176 ,  H01L2224/13178 ,  H01L2224/13181 ,  H01L2224/13184 ,  H01L2224/94 ,  H01L2924/01006 ,  H01L2924/01024 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/0104 ,  H01L2924/01044 ,  H01L2924/01045 ,  H01L2924/01047 ,  H01L2924/01073 ,  H01L2924/01074 ,  H01L2924/01077 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/1461 ,  H01L2924/15788 ,  H01L2924/181 ,  Y10T428/12056 ,  H01L2224/11 ,  H01L2924/00014 ,  H01L2924/00 ,  H01L2924/01046 ,  H01L2924/00012

Abstract: 　本発明は、基板と、前記基板上に形成された少なくとも一つの金属配線素材と、前記金属配線素材の表面上に形成された少なくとも１層の被覆層と、前記基板と前記金属配線素材との間に形成された下地金属膜と、からなり、前記金属配線素材を被転写物に転写させるための転写用基板であって、前記金属配線素材は、純度９９．９重量％以上、平均粒径０．０１μｍ～１．０μｍである金粉等の金属粉末を焼結してなる成形体であり、前記被覆層は、金等の所定の金属又は合金であって、前記金属配線素材と相違する組成の金属又は合金からなり、かつ、その合計厚さは１μｍ以下であり、前記下地金属膜は、金等の所定の金属又合金からなる転写用基板である。本発明に係る転写用基板は、転写法により被転写物に金属配線を形成する際に被転写物側の加熱温度を低くすることができる。

Abstract translation: 本发明是由基板形成的转印基板，在基板上形成的至少一种金属布线材料，形成在金属布线材料的表面上的至少一层涂层和基体金属膜， 形成在基板和金属布线材料之间，并且用于将金属布线材料转印到转印接收对象的目的。 金属布线材料是通过烧结纯度为99.9重量％以上，平均粒径为0.01〜1.0μm的金粉等金属粉末而得到的成型体。 涂层由诸如金或其合金的特定金属形成，所述特定金属或合金具有与金属布线材料不同的组成。 金属布线材料和涂层的总厚度为1μm以下。 贱金属膜由金等金属及其合金形成。 当通过转印方法在转印接收对象上形成金属布线时，本发明的转印衬底能够降低转印接收对象侧的加热温度。

公开(公告)号：WO2009066847A1

公开(公告)日：2009-05-28

申请号：PCT/KR2008/003624

申请日：2008-06-25

Applicant: SECRON CO., LTD. ,  OH, Jung-Bae

Inventor： OH, Jung-Bae

IPC: H01L21/66

CPC classification number: B23K3/0623 ,  B23K2201/40 ,  H01L21/681 ,  H01L21/6835 ,  H01L23/544 ,  H01L24/11 ,  H01L2223/54426 ,  H01L2223/54453 ,  H01L2224/05001 ,  H01L2224/05022 ,  H01L2224/05027 ,  H01L2224/0508 ,  H01L2224/05124 ,  H01L2224/05147 ,  H01L2224/05572 ,  H01L2224/056 ,  H01L2224/11003 ,  H01L2224/11334 ,  H01L2224/13099 ,  H01L2224/13111 ,  H01L2224/13139 ,  H01L2224/13144 ,  H01L2224/13147 ,  H01L2224/16 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01047 ,  H01L2924/01058 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/01093 ,  H01L2924/014 ,  H01L2924/00014

Abstract: In a method of aligning a wafer and a method of manufacturing a flip chip, a wafer on which a first alignment mark is formed and a template formed of an opaque material is prepared. The template has a through-hole formed at a position corresponding to that of the first alignment mark and a second alignment mark formed at a position spaced apart from the center of the through-hole by a first distance. The wafer and the template are disposed to be adjacent to each other, and a second distance between the first alignment mark observed through the through-hole and the second alignment mark is measured. After comparing the second distance with the first distance, and when the second distance is different from the first distance, at least one of the wafer and the template is moved to allow the second distance to be equal to the first distance.

Abstract translation: 在对准晶片的方法和制造倒装芯片的方法中，制备其上形成有第一对准标记的晶片和由不透明材料形成的模板。 模板具有形成在与第一对准标记相对应的位置处的通孔和形成在与通孔的中心间隔开第一距离的位置处的第二对准标记。 晶片和模板被设置为彼此相邻，并且测量通过通孔观察的第一对准标记与第二对准标记之间的第二距离。 在将第二距离与第一距离进行比较之后，当第二距离与第一距离不同时，移动晶片和模板中的至少一个以允许第二距离等于第一距离。

公开(公告)号：WO2006138491A3

公开(公告)日：2009-05-07

申请号：PCT/US2006023363

申请日：2006-06-14

Applicant: CUBIC WAFER INC ,  TREZZA JOHN

Inventor： TREZZA JOHN

IPC: H01L21/4763

CPC classification number: H01L24/94 ,  H01L21/6835 ,  H01L21/76898 ,  H01L23/427 ,  H01L23/48 ,  H01L23/481 ,  H01L23/49827 ,  H01L23/5389 ,  H01L23/552 ,  H01L23/66 ,  H01L24/11 ,  H01L24/13 ,  H01L24/24 ,  H01L24/27 ,  H01L24/75 ,  H01L24/81 ,  H01L25/0652 ,  H01L25/0657 ,  H01L25/50 ,  H01L2221/68368 ,  H01L2223/6616 ,  H01L2223/6622 ,  H01L2224/05001 ,  H01L2224/05022 ,  H01L2224/05023 ,  H01L2224/05026 ,  H01L2224/05027 ,  H01L2224/0508 ,  H01L2224/05147 ,  H01L2224/05568 ,  H01L2224/05572 ,  H01L2224/05573 ,  H01L2224/05644 ,  H01L2224/05655 ,  H01L2224/05664 ,  H01L2224/05666 ,  H01L2224/1147 ,  H01L2224/13099 ,  H01L2224/13609 ,  H01L2224/16 ,  H01L2224/24226 ,  H01L2224/274 ,  H01L2224/75305 ,  H01L2224/81136 ,  H01L2224/81193 ,  H01L2224/81801 ,  H01L2225/06513 ,  H01L2225/06524 ,  H01L2225/06527 ,  H01L2225/06541 ,  H01L2924/0001 ,  H01L2924/01004 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01012 ,  H01L2924/01013 ,  H01L2924/01015 ,  H01L2924/01018 ,  H01L2924/01022 ,  H01L2924/01023 ,  H01L2924/01024 ,  H01L2924/01025 ,  H01L2924/01027 ,  H01L2924/01029 ,  H01L2924/0103 ,  H01L2924/01032 ,  H01L2924/01033 ,  H01L2924/01042 ,  H01L2924/01046 ,  H01L2924/01047 ,  H01L2924/01049 ,  H01L2924/0105 ,  H01L2924/01051 ,  H01L2924/01061 ,  H01L2924/01073 ,  H01L2924/01074 ,  H01L2924/01075 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/04953 ,  H01L2924/09701 ,  H01L2924/10253 ,  H01L2924/10329 ,  H01L2924/14 ,  H01L2924/19041 ,  H01L2924/19043 ,  H01L2924/30105 ,  H01L2924/3011 ,  H01L2924/3025 ,  H01L2924/3512 ,  H01L2924/00 ,  H01L2924/00014

Abstract: A method performed on a semiconductor chip having a doped semiconductor material abutting a substrate involves creating a first via through at least a portion of the substrate extending from an outer side of the substrate towards the doped semiconductor material, the first via having a wall surface and a bottom, introducing a first electrically conductive material into the first via so as to create an electrically conductive path, creating a second via, aligned with the first via, extending from an outer surface of the doped portion of the semiconductor chip to the bottom, and introducing a second electrically conductive material into the second via so as to create an electrically conductive path.

Abstract translation: 在具有邻接衬底的掺杂半导体材料的半导体芯片上执行的方法包括通过从衬底的外侧向掺杂半导体材料延伸的至少部分衬底形成第一通孔，第一通孔具有壁表面和 将第一导电材料引入第一通孔中以形成导电路径，从半导体芯片的掺杂部分的外表面延伸到底部，产生与第一通孔对准的第二通孔， 并将第二导电材料引入第二通孔中，以便产生导电路径。

公开(公告)号：WO2006138494A3

公开(公告)日：2007-03-22

申请号：PCT/US2006023366

申请日：2006-06-14

Applicant: CUBIC WAFER INC ,  TREZZA JOHN

Inventor： TREZZA JOHN

IPC: H01L29/40

CPC classification number: H01L23/481 ,  H01L21/76898 ,  H01L24/11 ,  H01L25/0652 ,  H01L25/0657 ,  H01L25/50 ,  H01L2224/05001 ,  H01L2224/05022 ,  H01L2224/05023 ,  H01L2224/05026 ,  H01L2224/05027 ,  H01L2224/0508 ,  H01L2224/05147 ,  H01L2224/05568 ,  H01L2224/05572 ,  H01L2224/05573 ,  H01L2224/05644 ,  H01L2224/05655 ,  H01L2224/05664 ,  H01L2224/05666 ,  H01L2224/1147 ,  H01L2224/13099 ,  H01L2224/1358 ,  H01L2224/13609 ,  H01L2224/16 ,  H01L2224/24226 ,  H01L2224/75305 ,  H01L2225/06513 ,  H01L2225/06524 ,  H01L2225/06531 ,  H01L2225/06534 ,  H01L2225/06541 ,  H01L2225/06555 ,  H01L2924/01004 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01012 ,  H01L2924/01013 ,  H01L2924/01018 ,  H01L2924/01022 ,  H01L2924/01023 ,  H01L2924/01024 ,  H01L2924/01025 ,  H01L2924/01027 ,  H01L2924/01029 ,  H01L2924/0103 ,  H01L2924/01032 ,  H01L2924/01033 ,  H01L2924/01046 ,  H01L2924/01047 ,  H01L2924/01049 ,  H01L2924/01051 ,  H01L2924/01061 ,  H01L2924/01073 ,  H01L2924/01074 ,  H01L2924/01075 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/04953 ,  H01L2924/09701 ,  H01L2924/10253 ,  H01L2924/10329 ,  H01L2924/14 ,  H01L2924/19041 ,  H01L2924/19043 ,  H01L2924/30105 ,  H01L2924/3011 ,  H01L2924/3025 ,  H01L2924/00 ,  H01L2924/00014

Abstract: A method of creating a semiconductor chip having a substrate, a doped semiconductor material abutting the substrate and a device pad at an outer side of the doped semiconductor material involves creating a via through at least a portion of the substrate, the via having a periphery and a bottom at a location and depth sufficient to bring the via into proximity with the device pad but be physically spaced apart from the device pad, introducing an electrically conductive material into the via, and connecting the electrically conductive material to a signal source so the signal will deliberately be propagated from the electrically conductive material to the device pad without any direct electrical connection existing between the electrically conductive material and the device pad.

Abstract translation: 一种制造半导体芯片的方法，该半导体芯片具有衬底，与衬底相邻的掺杂半导体材料和在掺杂半导体材料的外侧的器件焊盘，包括通过衬底的至少一部分形成通孔，该通孔具有外围和 在足够的位置和深度处的底部，以使通孔靠近设备衬垫，但是物理地与器件衬垫隔开，将导电材料引入通孔，并将导电材料连接到信号源，使得信号 将有意地从导电材料传播到器件焊盘，而不会在导电材料和器件焊盘之间存在任何直接的电连接。

公开(公告)号：WO2006138490A2

公开(公告)日：2006-12-28

申请号：PCT/US2006023362

申请日：2006-06-14

Applicant: CUBIC WAFER INC ,  TREZZA JOHN ,  MISRA ABHAY

Inventor： TREZZA JOHN ,  MISRA ABHAY

IPC: H01L21/4763

CPC classification number: H01L21/76898 ,  H01L23/5389 ,  H01L24/11 ,  H01L24/24 ,  H01L25/0657 ,  H01L25/50 ,  H01L2224/05001 ,  H01L2224/05022 ,  H01L2224/05023 ,  H01L2224/05026 ,  H01L2224/05027 ,  H01L2224/0508 ,  H01L2224/05147 ,  H01L2224/05568 ,  H01L2224/05572 ,  H01L2224/05573 ,  H01L2224/05644 ,  H01L2224/05655 ,  H01L2224/05664 ,  H01L2224/05666 ,  H01L2224/1147 ,  H01L2224/13099 ,  H01L2224/13147 ,  H01L2224/13609 ,  H01L2224/16 ,  H01L2224/24226 ,  H01L2224/75305 ,  H01L2225/06513 ,  H01L2225/06524 ,  H01L2225/06531 ,  H01L2225/06534 ,  H01L2225/06541 ,  H01L2225/06589 ,  H01L2225/06596 ,  H01L2924/01004 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01012 ,  H01L2924/01013 ,  H01L2924/01018 ,  H01L2924/01022 ,  H01L2924/01023 ,  H01L2924/01024 ,  H01L2924/01025 ,  H01L2924/01027 ,  H01L2924/01029 ,  H01L2924/0103 ,  H01L2924/01032 ,  H01L2924/01033 ,  H01L2924/01046 ,  H01L2924/01047 ,  H01L2924/01049 ,  H01L2924/01051 ,  H01L2924/01073 ,  H01L2924/01074 ,  H01L2924/01075 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/04953 ,  H01L2924/09701 ,  H01L2924/10253 ,  H01L2924/10329 ,  H01L2924/14 ,  H01L2924/19041 ,  H01L2924/19043 ,  H01L2924/30105 ,  H01L2924/3011 ,  H01L2924/3025 ,  H01L2924/00 ,  H01L2924/00014

Abstract: A method of creating a unified chip involves performing front-end processing on a first wafer, the front end processing creating multiple devices on the wafer, performing back- end processing on a second wafer, the back end processing creating layers of interconnected metal traces arranged to interconnect at least some of the multiple devices to each other, and bonding the first wafer to the second wafer such that the multiple devices on the first wafer are interconnected to each other by the metal traces of the second wafer.

Abstract translation: 创建统一芯片的方法涉及在第一晶片上进行前端处理，前端处理在晶片上创建多个器件，在第二晶片上执行后端处理，后端处理产生互连的金属迹线层，布置 将所述多个设备中的至少一些彼此互连，以及将所述第一晶片接合到所述第二晶片，使得所述第一晶片上的所述多个器件通过所述第二晶片的金属迹线彼此互连。

公开(公告)号：WO2006138489A2

公开(公告)日：2006-12-28

申请号：PCT/US2006/023361

申请日：2006-06-14

Applicant: CUBIC WAFER, INC. ,  TREZZA, John

Inventor： TREZZA, John

IPC: H01L21/00

CPC classification number: H01L21/76898 ,  H01L23/481 ,  H01L24/11 ,  H01L24/13 ,  H01L24/75 ,  H01L24/81 ,  H01L2224/05001 ,  H01L2224/05022 ,  H01L2224/05023 ,  H01L2224/05026 ,  H01L2224/05027 ,  H01L2224/0508 ,  H01L2224/05147 ,  H01L2224/05568 ,  H01L2224/05572 ,  H01L2224/05573 ,  H01L2224/05644 ,  H01L2224/05655 ,  H01L2224/05664 ,  H01L2224/05666 ,  H01L2224/11462 ,  H01L2224/11464 ,  H01L2224/1147 ,  H01L2224/11902 ,  H01L2224/1308 ,  H01L2224/13082 ,  H01L2224/13083 ,  H01L2224/13084 ,  H01L2224/13144 ,  H01L2224/13147 ,  H01L2224/13155 ,  H01L2224/13166 ,  H01L2224/13184 ,  H01L2224/13609 ,  H01L2224/16 ,  H01L2224/16058 ,  H01L2224/16146 ,  H01L2224/16227 ,  H01L2224/16237 ,  H01L2224/81136 ,  H01L2224/81191 ,  H01L2224/81193 ,  H01L2224/81208 ,  H01L2224/81815 ,  H01L2924/00013 ,  H01L2924/01004 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01012 ,  H01L2924/01013 ,  H01L2924/01015 ,  H01L2924/01018 ,  H01L2924/01022 ,  H01L2924/01023 ,  H01L2924/01024 ,  H01L2924/01025 ,  H01L2924/01027 ,  H01L2924/01029 ,  H01L2924/0103 ,  H01L2924/01032 ,  H01L2924/01033 ,  H01L2924/01046 ,  H01L2924/01047 ,  H01L2924/01049 ,  H01L2924/0105 ,  H01L2924/01051 ,  H01L2924/01052 ,  H01L2924/01073 ,  H01L2924/01074 ,  H01L2924/01075 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/04953 ,  H01L2924/09701 ,  H01L2924/10253 ,  H01L2924/10329 ,  H01L2924/14 ,  H01L2924/19041 ,  H01L2924/19043 ,  H01L2924/30105 ,  H01L2924/3011 ,  H01L2924/3025 ,  H01L2924/00014 ,  H01L2224/45111 ,  H01L2224/13099 ,  H01L2924/00

Abstract: A chip unit has a stack of at least two electronic chips stacked one on top of the other, a through-chip connection within the stack, the through chip connection including a bounding material having an inner and outer perimeter, the inner perimeter defining an interior volume longitudinally extending through at least one of the at least two chips and at least partially into another of the at least two chips so as to form a tube extending between the one and the other of the chips, and an amount of working fluid hermetically sealed within the tube, the working fluid having a volume and being at a pressure such that the working fluid and tube will operate as a heat pipe and transfer heat from the stack of chips to the working fluid.

Abstract translation: 芯片单元具有堆叠在一起的另一个的至少两个电子芯片的堆叠，堆叠内的贯穿芯片连接，所述贯穿芯片连接包括具有内部和外部周边的边界材料，所述内部周边限定内部 纵向延伸穿过所述至少两个芯片中的至少一个并且至少部分地进入所述至少两个芯片中的另一个，以形成在所述一个和另一个芯片之间延伸的管，并且一定量的工作流体密封 在管内，工作流体具有体积并且处于压力，使得工作流体和管将作为热管进行操作，并将热量从芯片堆传递到工作流体。

公开(公告)号：WO2006138426A2

公开(公告)日：2006-12-28

申请号：PCT/US2006/023250

申请日：2006-06-14

Applicant: CUBIC WAFER, INC. ,  CALLAHAN, Jon ,  TREZZA, John ,  DUDOFF, Gregory

Inventor： CALLAHAN, Jon ,  TREZZA, John ,  DUDOFF, Gregory

IPC: H01L23/48

CPC classification number: H01L24/13 ,  H01L21/76898 ,  H01L23/48 ,  H01L23/481 ,  H01L24/11 ,  H01L24/75 ,  H01L25/0657 ,  H01L25/50 ,  H01L2224/05001 ,  H01L2224/05022 ,  H01L2224/05023 ,  H01L2224/05026 ,  H01L2224/05027 ,  H01L2224/0508 ,  H01L2224/05147 ,  H01L2224/05568 ,  H01L2224/05572 ,  H01L2224/05573 ,  H01L2224/05644 ,  H01L2224/05655 ,  H01L2224/05664 ,  H01L2224/05666 ,  H01L2224/1147 ,  H01L2224/13099 ,  H01L2224/13147 ,  H01L2224/13609 ,  H01L2224/16 ,  H01L2224/24226 ,  H01L2224/75305 ,  H01L2224/75315 ,  H01L2225/06513 ,  H01L2225/06541 ,  H01L2225/06593 ,  H01L2924/01004 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01012 ,  H01L2924/01013 ,  H01L2924/01015 ,  H01L2924/01018 ,  H01L2924/01022 ,  H01L2924/01023 ,  H01L2924/01024 ,  H01L2924/01025 ,  H01L2924/01027 ,  H01L2924/01029 ,  H01L2924/0103 ,  H01L2924/01032 ,  H01L2924/01033 ,  H01L2924/01042 ,  H01L2924/01046 ,  H01L2924/01047 ,  H01L2924/01049 ,  H01L2924/01051 ,  H01L2924/01073 ,  H01L2924/01074 ,  H01L2924/01075 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/04953 ,  H01L2924/09701 ,  H01L2924/10253 ,  H01L2924/10329 ,  H01L2924/14 ,  H01L2924/19041 ,  H01L2924/19043 ,  H01L2924/30105 ,  H01L2924/3011 ,  H01L2924/3025 ,  H01L2924/00 ,  H01L2924/00014

Abstract: A chip contact functionally having an IC pad, a barrier layer over the IC pad, and a malleable material over the barrier layer. An alternative chip contact functionally having an IC pad, a barrier layer over the IC pad, and a rigid material over the barrier layer.

Abstract translation: 芯片接触器在功能上具有IC焊盘，IC焊盘上的阻挡层，以及在阻挡层上方的可延展材料。 替代的芯片接触器在功能上具有IC焊盘，IC焊盘上的阻挡层以及阻挡层上的刚性材料。

公开(公告)号：WO2006138423A2

公开(公告)日：2006-12-28

申请号：PCT/US2006023246

申请日：2006-06-14

Applicant: CUBIC WAFER INC ,  TREZZA JOHN ,  CALLAHAN JOHN ,  DUDOFF GREGORY

Inventor： TREZZA JOHN ,  CALLAHAN JOHN ,  DUDOFF GREGORY

IPC: H01L23/52

CPC classification number: H01L21/6836 ,  H01L21/6835 ,  H01L21/76898 ,  H01L23/427 ,  H01L23/48 ,  H01L23/481 ,  H01L23/49827 ,  H01L23/552 ,  H01L24/11 ,  H01L24/13 ,  H01L24/75 ,  H01L24/81 ,  H01L25/0652 ,  H01L25/0657 ,  H01L25/50 ,  H01L2221/68327 ,  H01L2221/6834 ,  H01L2221/68359 ,  H01L2221/68363 ,  H01L2223/6616 ,  H01L2224/05001 ,  H01L2224/05022 ,  H01L2224/05023 ,  H01L2224/05026 ,  H01L2224/05027 ,  H01L2224/0508 ,  H01L2224/05147 ,  H01L2224/05568 ,  H01L2224/05572 ,  H01L2224/05573 ,  H01L2224/05644 ,  H01L2224/05664 ,  H01L2224/05666 ,  H01L2224/1147 ,  H01L2224/13012 ,  H01L2224/13099 ,  H01L2224/13147 ,  H01L2224/13609 ,  H01L2224/16 ,  H01L2224/75305 ,  H01L2224/81193 ,  H01L2224/8121 ,  H01L2224/81815 ,  H01L2225/06513 ,  H01L2225/06524 ,  H01L2225/06541 ,  H01L2225/06589 ,  H01L2225/06593 ,  H01L2225/06596 ,  H01L2924/01004 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01012 ,  H01L2924/01013 ,  H01L2924/01015 ,  H01L2924/01018 ,  H01L2924/01022 ,  H01L2924/01023 ,  H01L2924/01024 ,  H01L2924/01025 ,  H01L2924/01027 ,  H01L2924/01029 ,  H01L2924/0103 ,  H01L2924/01032 ,  H01L2924/01033 ,  H01L2924/01042 ,  H01L2924/01046 ,  H01L2924/01047 ,  H01L2924/01049 ,  H01L2924/0105 ,  H01L2924/01051 ,  H01L2924/01073 ,  H01L2924/01074 ,  H01L2924/01075 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/04953 ,  H01L2924/09701 ,  H01L2924/10253 ,  H01L2924/10329 ,  H01L2924/14 ,  H01L2924/19041 ,  H01L2924/19043 ,  H01L2924/30105 ,  H01L2924/3011 ,  H01L2924/3025 ,  H01L2924/00 ,  H01L2924/00014

Abstract: A method of electrically joining a first contact on a first wafer with a second contact on a second wafer, the first contact, a rigid material, and the second contact, a material that is malleable relative to the rigid material, such that when brought together the rigid material will penetrate the malleable material, the rigid and malleable materials both being electrically conductive involves bringing the rigid material into contact with the malleable material, applying a force to one of the first contact or the second contact so as to cause the rigid material to penetrate the malleable material, heating the rigid and malleable material so as to cause the malleable material to soften, and constraining the malleable material to within a pre-specified area.

Abstract translation: 一种将第一晶片上的第一触点与第二晶片上的第二触点电连接的方法，所述第一触点，刚性材料和所述第二触点，相对于所述刚性材料是可延展的材料，使得当被连接在一起时 刚性材料将穿透可延展材料，刚性和可延展材料都是导电的，包括使刚性材料与可延展材料接触，向第一接触件或第二接触件中的一个施加力，从而使刚性材料 穿透可延展材料，加热刚性和有韧性的材料，以使有韧性的材料软化，并将可延展材料限制在预先指定的区域内。