公开(公告)号：WO2018058548A1

公开(公告)日：2018-04-05

申请号：PCT/CN2016/101130

申请日：2016-09-30

申请人： INTEL CORPORATION ,  DING, Zhicheng ,  LIU, Bin ,  SHE, Yong ,  TAN, Aiping ,  DENG, Li

发明人： DING, Zhicheng ,  LIU, Bin ,  SHE, Yong ,  TAN, Aiping ,  DENG, Li

IPC分类号： H01L25/00

摘要： A system in package includes a stair-stacked memory module that is stacked vertically with respect to a processor die. A spacer is used adjacent to the processor die to create a bridge for the stair-stacked memory module. Each memory die in the stair-stacked memory module includes a vertical bond wire that emerges from a matrix for connection. The matrix encloses the stair-stacked memory module and at least a portion of the processor die.

摘要翻译： 封装中的系统包括相对于处理器裸片垂直堆叠的阶梯式堆叠式存储器模块。 邻近处理器芯片使用垫片为阶梯堆叠的内存模块创建桥接。 楼梯式堆叠存储器模块中的每个存储器裸片包括从矩阵中露出的用于连接的垂直接合线。 矩阵包围阶梯式堆叠的存储器模块和至少一部分处理器裸片。

公开(公告)号：WO2019061166A1

公开(公告)日：2019-04-04

申请号：PCT/CN2017/104029

申请日：2017-09-28

申请人： INTEL CORPORATION ,  XU, Zhijun ,  LIU, Bin ,  SHE, Yong ,  DING, Zhicheng

发明人： XU, Zhijun ,  LIU, Bin ,  SHE, Yong ,  DING, Zhicheng

IPC分类号： H01L25/00 ,  H01L23/13

摘要： An apparatus, comprising an IC package having a first surface, a second surface opposing the first surface, and at least four sidewalls extending orthogonally from a perimeter of the first surface to a perimeter of the second surface, and one or more electronic devices disposed on one or more of the at least four sidewalls.

公开(公告)号：WO2018058416A1

公开(公告)日：2018-04-05

申请号：PCT/CN2016/100760

申请日：2016-09-29

申请人： INTEL CORPORATION ,  DING, Zhicheng ,  LIU, Bin ,  SHE, Yong ,  TAN, Aiping ,  DENG, Li

发明人： DING, Zhicheng ,  LIU, Bin ,  SHE, Yong ,  TAN, Aiping ,  DENG, Li

IPC分类号： H01L23/522

摘要： A pre-packaged stair-stacked memory module is mounted on a board with at least one additional component. A stair-stacked memory module includes a plurality of memory dice that are stacked vertically with respect to a processor die. A spacer is used adjacent to the processor die to create a bridge for the stair-stacked memory module. Each memory die in the stair-stacked memory module includes a vertical bond wire that emerges from a matrix for connection. The matrix encloses the stair-stacked memory module and at least a portion of the processor die. The matrix might also enclose the at least one additional component.

摘要翻译：

预先封装的阶梯式堆叠内存模块安装在至少有一个附加组件的电路板上。 楼梯堆叠的存储器模块包括相对于处理器裸片垂直堆叠的多个存储器裸片。 邻近处理器芯片使用垫片为阶梯堆叠的内存模块创建桥接。 楼梯式堆叠存储器模块中的每个存储器裸片包括从矩阵中露出的用于连接的垂直接合线。 矩阵包围阶梯堆叠的存储器模块和处理器裸片的至少一部分。 矩阵也可能包含至少一个附加组件。

公开(公告)号：WO2020118558A1

公开(公告)日：2020-06-18

申请号：PCT/CN2018/120572

申请日：2018-12-12

申请人： INTEL CORPORATION ,  DING, Zhicheng ,  LIU, Bin ,  SHE, Yong ,  XU, Zhijun

发明人： DING, Zhicheng ,  LIU, Bin ,  SHE, Yong ,  XU, Zhijun

IPC分类号： H01L23/525

摘要： Embodiments described herein provide techniques of forming an interconnect structure using lithographic and deposition processes. The interconnect structure can be used to couple components of a semiconductor package. For one example, a semiconductor package includes a die stack and an interconnect structure formed on the die stack. The die stack comprises a plurality of dies. Each die in the die stack comprises: a first surface; a second surface opposite the first surface; sidewall surfaces coupling the first surface to the second surface; and a pad on the first surface. A one sidewall surface of one of the dies has a sloped profile. The semiconductor package also includes an interconnect structure positioned on the first surfaces and the sidewall with the sloped profile. In this semiconductor package, the interconnect structure electrically couples the pad on each of the dies to each other.

公开(公告)号：WO2018112687A1

公开(公告)日：2018-06-28

申请号：PCT/CN2016/110701

申请日：2016-12-19

申请人： INTEL CORPORATION ,  LIU, Bin ,  DING, Zhicheng ,  SHE, Yong ,  TAN, Aiping ,  GUO, Mao

发明人： LIU, Bin ,  DING, Zhicheng ,  SHE, Yong ,  TAN, Aiping ,  GUO, Mao

IPC分类号： H01L25/00

摘要： Disclosed herein are integrated circuit (IC) die stacks, as well as related apparatuses and methods. For example, in some embodiments, an IC package may include: a package substrate having a substrate conductive contact; a first die coupled to the package substrate, wherein the first die has a first face and an opposing second face, the second face of the first die is between the first face of the first die and the package substrate, and the first die has a first conductive contact at the first face of the first die; a second die coupled to the first die, wherein the second die has a second conductive contact facing the first face of the first die; and a bondwire between the first conductive contact and the substrate conductive contact, wherein the bondwire is also in electrical contact with the second conductive contact.

公开(公告)号：WO2017107174A1

公开(公告)日：2017-06-29

申请号：PCT/CN2015/098867

申请日：2015-12-25

申请人： INTEL CORPORATION ,  DING, Zhicheng ,  LIU, Bin

发明人： DING, Zhicheng ,  LIU, Bin

IPC分类号： H01L25/16

CPC分类号： H01L25/16 ,  H01L22/14 ,  H01L24/32 ,  H01L24/48 ,  H01L24/73 ,  H01L24/92 ,  H01L25/18 ,  H01L25/50 ,  H01L2224/32145 ,  H01L2224/32225 ,  H01L2224/48091 ,  H01L2224/48147 ,  H01L2224/48227 ,  H01L2224/73265 ,  H01L2224/92247 ,  H01L2225/0651 ,  H01L2225/06562 ,  H01L2924/1433 ,  H01L2924/1434 ,  H01L2924/15311 ,  H01L2924/19103 ,  H01L2924/19105 ,  H01L2924/00014 ,  H01L2924/00012 ,  H01L2224/32245 ,  H01L2224/48247 ,  H01L2924/00

摘要： A system in package and method for making a system in package. A plurality of passive devices are coupled to an interposer. A molding compound envelopes the plurality of passive devices and defines a platform having a substantially planar surface. The interposer is coupled to a substrate. A plurality of integrated circuit dies are coupled in a stack to the planar surface.

摘要翻译：

封装中的系统和封装中的系统。 多个无源器件耦合到插入器。 模制化合物包封多个无源器件并限定具有基本上平坦的表面的平台。 内插器耦合到衬底。 多个集成电路管芯以堆叠方式耦合到平面表面。

公开(公告)号：WO2017049585A1

公开(公告)日：2017-03-30

申请号：PCT/CN2015/090716

申请日：2015-09-25

申请人： INTEL CORPORATION ,  SHE, Yong ,  MEYERS, John G. ,  DING, Zhicheng ,  PATTEN, Richard

发明人： SHE, Yong ,  MEYERS, John G. ,  DING, Zhicheng ,  PATTEN, Richard

IPC分类号： H01L25/065 ,  H01L23/488

CPC分类号： H01L23/488 ,  H01L23/5389 ,  H01L24/19 ,  H01L24/20 ,  H01L24/32 ,  H01L24/73 ,  H01L24/92 ,  H01L2224/12105 ,  H01L2224/214 ,  H01L2224/32145 ,  H01L2224/32225 ,  H01L2224/32245 ,  H01L2224/73217 ,  H01L2224/73267 ,  H01L2224/83007 ,  H01L2224/92174 ,  H01L2224/92244 ,  H01L2924/14 ,  H01L2924/18162

摘要： Techniques and mechanisms for interconnecting stacked integrated circuit (IC) dies. In an embodiment, a first end of a wire is coupled to a first IC die of a stack, where a second end of the wire is further anchored to the stack independent of the coupled first end. A package material is subsequently disposed around IC dies of the stack and a first portion of the wire that includes the first end. Two-point anchoring of the wire to the stack aids in providing mechanical support to resist movement that might otherwise displace and/or deform the wire while the package material is deposited. In another embodiment, the first portion of the wire is separated from the rest of the wire, and a redistribution layer is coupled to the first portion to enable interconnection between the first IC die and another IC die of the stack.

摘要翻译： 互连堆叠集成电路（IC）裸片的技术和机制。 在一个实施例中，线的第一端耦合到堆叠的第一IC芯片，其中线的第二端进一步锚定到堆叠，而与耦合的第一端无关。 随后将包装材料设置在堆叠的IC管芯周围，并且包括第一端的电线的第一部分。 将电线的两点锚定到堆叠有助于提供机械支撑以阻止运动，否则在包装材料沉积时可能使电线移动和/或变形。 在另一个实施例中，导线的第一部分与导线的其余部分分离，再分布层耦合到第一部分，以实现第一IC裸片与叠层的另一IC芯片之间的互连。

公开(公告)号：WO2020168552A1

公开(公告)日：2020-08-27

申请号：PCT/CN2019/075875

申请日：2019-02-22

申请人： INTEL CORPORATION ,  TANG, Xiaoying ,  DING, Zhicheng ,  BIN, Liu ,  SHE, Yong ,  XU, Zhijun

发明人： TANG, Xiaoying ,  DING, Zhicheng ,  BIN, Liu ,  SHE, Yong ,  XU, Zhijun

IPC分类号： H01L23/488

摘要： Embodiments include semiconductor packages and a method of forming the semiconductor packages. A semiconductor package includes a package substrate with a top surface, a corner portion, and a plurality of solder balls on the top surface of the package substrate. The semiconductor package also includes a pattern on the corner portion of the package substrate. The pattern may have a width substantially equal to a width of the solder balls. The pattern may also include a continuous line having solder materials. The semiconductor package may include a plurality of conductive pads on the package substrate. The conductive pads may be coupled to the pattern. The pattern may have a z-height that is substantially equal to a z-height of the solder balls, and have one or more outer edges, where the outer edges of the pattern are sidewalls. The sidewalls of the pattern may be substantially vertical or tapered sidewalls.

公开(公告)号：WO2018112914A1

公开(公告)日：2018-06-28

申请号：PCT/CN2016/111785

申请日：2016-12-23

申请人： INTEL CORPORATION

发明人： DING, Zhicheng ,  SHE, Yong ,  LIU, Bin ,  TAN, Aiping ,  DENG, Li

IPC分类号： H01L25/065 ,  H01L23/00

摘要： A system in package includes a memory-die stack in memory module that is stacked vertically with respect to a processor die. Each memory die in the memory-die stack includes a vertical bond wire that emerges from a matrix for connection. Some configurations include the vertical bond wire emerging orthogonally beginning from a bond-wire pad. The matrix encloses the memory-die stack, the spacer, and at least a portion of the processor die.

公开(公告)号：WO2018119782A1

公开(公告)日：2018-07-05

申请号：PCT/CN2016/112717

申请日：2016-12-28

申请人： INTEL CORPORATION

发明人： TAN, Aiping ,  LIU, Bin ,  DENG, Li ,  SHE, Yong ,  DING, Zhicheng ,  GUO, Mao

IPC分类号： H01L23/31 ,  H01L25/00 ,  H01L21/52

摘要： Techniques for providing an integrated circuit package that avoids or eliminates x-y area and z-height compared to conventional integrated circuit packages. In certain examples, an example package can utilize a substrate with an opening and bottom side or sidewall terminations to avoid adding addition x-y substrate area or z-axis package height associated with an integrated circuit die of a stack of integrated circuit dies of the package.