公开(公告)号：WO2003081974A3

公开(公告)日：2003-10-02

申请号：PCT/JP2003/003533

申请日：2003-03-24

Applicant: MATSUSHITA ELECTRIC INDUSTRIAL CO., LTD.

Inventor： HAJI, Hiroshi ,  HIRAKAWA, Toshiro

IPC: H01L21/00

Abstract: The present invention provides an electronic component mounting apparatus, wherein a high speed operation can be provided by simplifying the structure of a mounting head and wherein the working efficiency can be improved by eliminating the use of the mounting head for a coating process. In the electronic component mounting apparatus, a flux is coated on chips supplied to an electronic component feeding unit while bump formation faces are directed upward. The chips are mounted on a substrate. A holding head receives the chips extracted from an adhesive sheet by a mounting head and is inverted relative to a stage on which a flux is spread. As a result, the bumps of the chips are covered with the flux and are flattened, and after the holding head is returned to the original stage, the chips on the stage are extracted and mounted on the substrate by the mounting head.

公开(公告)号：WO2004071149A1

公开(公告)日：2004-08-19

申请号：PCT/JP2004/001340

申请日：2004-02-09

Applicant: MATSUSHITA ELECTRIC INDUSTRIAL CO., LTD. ,  HAJI, Hiroshi

Inventor： HAJI, Hiroshi

IPC: H05K13/04

CPC classification number: H01L24/81 ,  H01L24/75 ,  H05K13/08 ,  Y10T29/49131

Abstract: In an electronic component mounting method in which electronic components are sucked/held by plural respective nozzles provided on a mounting head so as to be mounted on electronic component mounting portions of a board, such a mounting operation is sequentially carried out as to all of the electronic components, in which the electronic components, are sucked/held by the plural nozzles; an electronic component sucked/held by one of the plural nozzles is provisionally positioned above one electronic component mounting portion; both this electronic component and the electronic component mounting portion are observed by an observation head which is located between the board and the mounting head; a relative position detecting operation for detecting a relative positional relationship between this electronic component and the electronic component mounting portion is carried out as to all of the electronic components held by the mounting head; and the electronic component is positioned with respect to the electronic component mounting portion so as to be mounted thereon while the detected relative positional relationship is reflected

Abstract translation: 在电子部件安装方法中，电子部件由设置在安装头上的多个喷嘴吸引/保持以安装在电路板的电子部件安装部上，这样的安装操作依次执行于所有 其中电子部件被多个喷嘴吸住/保持的电子部件; 由多个喷嘴中的一个吸引/保持的电子部件临时定位在一个电子部件安装部上方; 通过位于板和安装头之间的观察头来观察该电子部件和电子部件安装部分; 对于由安装头保持的所有电子部件，执行用于检测该电子部件与电子部件安装部之间的相对位置关系的相对位置检测动作。 并且电子部件相对于电子部件安装部被定位成安装在其上，同时反映检测到的相对位置关系

公开(公告)号：WO2003001558A1

公开(公告)日：2003-01-03

申请号：PCT/JP2002/006294

申请日：2002-06-24

Applicant: MATSUSHITA ELECTRIC INDUSTRIAL CO., LTD.

Inventor： ARITA, Kiyoshi ,  IWAI, Tetsuhiro ,  HAJI, Hiroshi ,  SAKEMI, Shoji

IPC: H01J37/32

CPC classification number: H01L21/6835 ,  H01J37/3244 ,  H01J37/32532 ,  H01L21/304 ,  H01L21/3065 ,  H01L21/67092 ,  H01L21/6836 ,  H01L21/78 ,  H01L2221/68327 ,  H01L2221/6834

Abstract: In a plasma treating apparatus, a ceramic porous substance having a three-dimensional network structure in which a frame portion (18a) formed of ceramic containing alumina is provided continuously like a three-dimensional network is used for the material of an electrode member (17) for the plasma treating apparatus to be attached to the front surface of a gas supplying port of an electrode for plasma generation, and a gas for plasma generation is caused to pass through a hole portion (18b) formed irregularly in the three-dimensional network structure. Consequently, the distribution of the gas to be supplied is made uniform to prevent an abnormal discharge so that uniform etching having no variation can be carried out.

Abstract translation: 在等离子体处理装置中，使用具有三维网状结构的陶瓷多孔物质，其中由含有氧化铝的陶瓷形成的框架部分（18a）连续地设置为三维网络，用于电极部件（17）的材料 ），用于等离子体处理装置附着到用于等离子体产生的电极的气体供应口的前表面，并且使等离子体产生的气体通过在三维网络中不规则形成的孔部分（18b） 结构体。 因此，供给气体的分布均匀，以防止异常放电，从而可以进行不变化的均匀蚀刻。

公开(公告)号：WO2008081968A1

公开(公告)日：2008-07-10

申请号：PCT/JP2007/075368

申请日：2007-12-26

Applicant: MATSUSHITA ELECTRIC INDUSTRIAL CO., LTD. ,  ARITA, Kiyoshi ,  HAJI, Hiroshi

Inventor： ARITA, Kiyoshi ,  HAJI, Hiroshi

IPC: H01L21/78 ,  H01L21/308 ,  H01L21/304

CPC classification number: H01L21/78 ,  H01L21/304 ,  H01L21/67092

Abstract: An object is to provide a manufacturing method of a semiconductor chip, by which while a semiconductor wafer is not broken when the semiconductor wafer is transported before plasma dicing is carried out, a time required for the plasma dicing can be shortened, so that a manufacturing efficiency of the semiconductor chips can be improved. After a resist film 6 has been formed on a ground rear plane 1q of a semiconductor wafer 1, partial portions (6a and 1b) of cutting margin areas (6a, 1b, 1c, 3c) along dicing lines 2 are removed by a blade 13 corresponding to a mechanical cutting means, and thickness "t" of remaining cutting margin areas 1c of the semiconductor wafer 1 along a thickness direction thereof are made thinner, which never causes any problem when the semiconductor wafer 1 is transported. Thereafter, all of the remaining cutting margin areas (1c, 3a) are removed by performing a plasma etching process.

Abstract translation: 本发明的目的是提供一种半导体芯片的制造方法，通过该半导体芯片的制造方法，在半导体晶片在进行等离子体切割之前被输送时半导体晶片不破裂的情况下，可以缩短等离子体切割所需的时间，从而制造 可以提高半导体芯片的效率。 在半导体晶片1的接地背面1q上形成抗蚀剂膜6之后，沿着切割线2切割边缘区域（6a，1b，1c，3c）的部分部分（6a和1b）被刀片13 对应于机械切割装置，并且半导体晶片1的厚度方向上的剩余切割边缘区域1c的厚度“t”变薄，当半导体晶片1被输送时，这不会产生任何问题。 此后，通过进行等离子体蚀刻处理除去所有剩余的切割边缘区域（1c，3a）。

公开(公告)号：WO2006009286A1

公开(公告)日：2006-01-26

申请号：PCT/JP2005/013673

申请日：2005-07-20

Applicant: MATSUSHITA ELECTRIC INDUSTRIAL CO., LTD. ,  ARITA, Kiyoshi ,  HAJI, Hiroshi ,  NODA, Kazuhiro ,  NAKAGAWA, Akira ,  NISHINAKA, Teruaki

Inventor： ARITA, Kiyoshi ,  HAJI, Hiroshi ,  NODA, Kazuhiro ,  NAKAGAWA, Akira ,  NISHINAKA, Teruaki

IPC: H01L21/78

CPC classification number: G03F7/70433 ,  H01L21/78

Abstract: With use of a length-dimension of a second-line-segment of a unit-device-formation-region as an arrangement interval, a plurality of parallel lines are disposed in a device-formation-effective-region on a wafer so as to form a plurality of parallel-line-partition-regions, the unit-device-formation-regions are arranged in each of the parallel-line-partition-regions independently of and separately from other parallel-line-partition-regions so that the acquisition number of the unit-device-formation-regions is maximized, and an arrangement of the respective unit-device-formation-regions in the respective parallel-line-partition-regions is determined as an arrangement of the entire device-formation-effective-region.

Abstract translation: 利用单元器件形成区域的二线段的长度尺寸作为布置间隔，在晶片上的器件形成有效区域中设置多条平行线，以便 形成多个平行线分隔区域，单元器件形成区域与其他平行线分隔区域独立地并且与其它平行线分隔区域分开布置在每个并行线分隔区域中，使得获取 单位元件形成区域的数量最大化，并且各个平行线分隔区域中的各个单位元件形成区域的布置被确定为整个器件形成有效的区域的布置， 地区。

公开(公告)号：WO2003001557A1

公开(公告)日：2003-01-03

申请号：PCT/JP2002/006293

申请日：2002-06-24

Applicant: MATSUSHITA ELECTRIC INDUSTRIAL CO., LTD. ,  KROSAKI HARIMA CORPORATION

Inventor： ARITA, Kiyoshi ,  IWAI, Tetsuhiro ,  HAJI, Hiroshi ,  SAKEMI, Shoji ,  MATANO, Taiji ,  SATOU, Nobuhiro

IPC: H01J37/32

CPC classification number: C23C16/45568 ,  H01J37/32009 ,  H01J37/3244 ,  H01J37/32532 ,  H01L21/3065

Abstract: In a plasma treating apparatus, a ceramic porous substance having a three-dimensional network structure in which a frame portion formed of ceramic containing alumina is provided continuously like a three-dimensional network is used for the material of an electrode member for the plasma treating apparatus to be attached to the front surface of a gas supplying port of an electrode for plasma generation, and a gas for plasma generation is caused to pass through a hole portion formed irregularly in the three-dimensional network structure. Consequently, the distribution of the gas to be supplied is made uniform to prevent an abnormal discharge so that uniform etching having no variation can be carried out.

Abstract translation: 在等离子体处理装置中，使用具有三维网状结构的陶瓷多孔物质，其中由含有氧化铝的陶瓷形成的框架部分连续地设置为三维网络，用于等离子体处理装置的电极部件的材料 附着于等离子体产生用电极的气体供给口的前表面，使等离子体产生用气体通过三维网络结构中不规则形成的孔部。 因此，供给气体的分布均匀，以防止异常放电，从而可以进行不变化的均匀蚀刻。

公开(公告)号：WO2006013910A1

公开(公告)日：2006-02-09

申请号：PCT/JP2005/014261

申请日：2005-07-28

Applicant: MATSUSHITA ELECTRIC INDUSTRIAL CO., LTD. ,  HAJI, Hiroshi ,  ARITA, Kiyoshi ,  NISHINAKA, Teruaki

Inventor： HAJI, Hiroshi ,  ARITA, Kiyoshi ,  NISHINAKA, Teruaki

IPC: H01L21/78

CPC classification number: H01L21/6835 ,  H01L21/6836 ,  H01L21/78 ,  H01L23/544 ,  H01L2221/68327 ,  H01L2221/6834 ,  H01L2221/68359 ,  H01L2223/54473 ,  H01L2924/0002 ,  H01L2924/00

Abstract: On a mask placement-side surface of a semiconductor wafer in which a plurality of semiconductor devices are formed, a mask is placed, while dicing lines for dicing the semiconductor wafer into the respective separate semiconductor devices are defined and a surface of a flawed semiconductor device among the respective semiconductor devices is partially exposed, and then plasma etching is applied to the mask placement-side surface of the semiconductor wafer so as to dice the semiconductor wafer into the respective semiconductor devices along the defined dicing lines, and an exposed portion of the flawed semiconductor device is removed so as to form a removed portion as a flawed semiconductor device distinguishing mark.

Abstract translation: 在其中形成有多个半导体器件的半导体晶片的掩模放置侧表面上，设置掩模，同时定义用于将半导体晶片切割成各自的分离的半导体器件的切割线和有缺陷的半导体器件的表面 在各个半导体器件中部分曝光，然后将等离子体蚀刻施加到半导体晶片的掩模放置侧表面，以便沿着限定的切割线将半导体晶片切割成各个半导体器件，并且将暴露部分 去除有缺陷的半导体器件，以形成作为有缺陷的半导体器件区分标记的去除部分。

公开(公告)号：WO2005101943A2

公开(公告)日：2005-10-27

申请号：PCT/JP2005/007276

申请日：2005-04-08

Applicant: MATSUSHITA ELECTRIC INDUSTRIAL CO., LTD. ,  HAJI, Hiroshi ,  OZONO, Mitsuru

Inventor： HAJI, Hiroshi ,  OZONO, Mitsuru

IPC: H05K13/00

CPC classification number: H01L21/67144 ,  H01L21/67132 ,  H01L21/681 ,  H01L21/6838 ,  Y10T29/4913 ,  Y10T29/49131 ,  Y10T29/49144 ,  Y10T29/53039 ,  Y10T29/53174 ,  Y10T29/53178

Abstract: In an electronic component mounting process for mounting electronic components (6) to a substrate (13), each of the electronic components (6) having an adhesive layer on a surface to be bonded to the substrate (13) is picked up with suction nozzle (33a) provided with individual heater (49), and a time taken for the mounting operation is so allotted that a first heating time (T1) of a duration from a moment when the suction nozzle (33a) comes into contact with the electronic component (6) for picking it up till another moment immediately before it begins a mounting motion to the substrate (13) is longer than a second heating time (T2) of a duration from the moment when the suction nozzle (33a) begins the mounting motion till another moment when it leaves the electronic component (6) mounted to the substrate (13).

Abstract translation: 在将电子部件（6）安装到基板（13）的电子部件安装工序中，在与基板（13）接合的表面上具有粘接层的各电子部件（6）被吸引吸嘴 （33a），设置有单独的加热器（49），并且分配用于安装操作的时间，使得从吸嘴（33a）与电子部件接触的时刻的持续时间的第一加热时间（T1） （6），用于将其拾取直到其开始向衬底（13）的安装运动之前的另一时刻长于从吸嘴（33a）开始安装运动的时刻开始的持续时间的第二加热时间（T2） 直到其离开安装到基板（13）的电子部件（6）的另一时刻。

公开(公告)号：WO2003081974A2

公开(公告)日：2003-10-02

申请号：PCT/JP2003/003533

申请日：2003-03-24

Applicant: MATSUSHITA ELECTRIC INDUSTRIAL CO., LTD.

Inventor： HAJI, Hiroshi ,  HIRAKAWA, Toshiro

IPC: H05K13/00

CPC classification number: H01L21/6715 ,  H01L21/67144 ,  H01L21/681 ,  H01L24/75 ,  Y10T29/53178 ,  Y10T29/53183 ,  Y10T29/53191

Abstract: The present invention provides an electronic component mounting apparatus, wherein a high speed operation can be provided by simplifying the structure of a mounting head and wherein the working efficiency can be improved by eliminating the use of the mounting head for a coating process. In the electronic component mounting apparatus, a flux is coated on chips supplied to an electronic component feeding unit while bump formation faces are directed upward. The chips are mounted on a substrate. A holding head receives the chips extracted from an adhesive sheet by a mounting head and is inverted relative to a stage on which a flux is spread. As a result, the bumps of the chips are covered with the flux and are flattened, and after the holding head is returned to the original stage, the chips on the stage are extracted and mounted on the substrate by the mounting head.

Abstract translation: 本发明提供一种电子部件安装装置，其中通过简化安装头的结构可以提供高速操作，并且其中可以通过消除使用用于涂覆过程的安装头来提高工作效率。 在电子部件安装装置中，将焊剂涂布在供给电子部件供给部的芯片上，同时将凸起形成面朝向上方。 芯片安装在基板上。 保持头通过安装头接收从粘合片提取的碎片，并且相对于其上扩散有焊剂的台倒置。 结果，芯片的凸起被焊剂覆盖并被压平，并且在保持头返回到原始台之后，台架上的芯片被提取并通过安装头安装在基板上。

公开(公告)号：WO2008044778A1

公开(公告)日：2008-04-17

申请号：PCT/JP2007/070016

申请日：2007-10-05

Applicant: MATSUSHITA ELECTRIC INDUSTRIAL CO., LTD. ,  ARITA, Kiyoshi ,  HAJI, Hiroshi

Inventor： ARITA, Kiyoshi ,  HAJI, Hiroshi

IPC: H01L21/78

CPC classification number: H01L21/78 ,  B23K2203/42 ,  B23K2203/50 ,  H01L24/743 ,  H01L2224/743 ,  H01L2924/12042 ,  H01L2924/00

Abstract: After a film layer 6 formed from a die attach film 4 and a UV tape 5 has been provided as a mask on a semiconductor wafer 1, boundary trenches 7 for partitioning semiconductor elements 2 formed on a circuit pattern formation surface 1a are formed in the film layer 6, thereby making a surface 1c of a semiconductor wafer 1 exposed. The exposed surface 1c of the semiconductor wafer 1 in the boundary trenches 7 is etched by means of plasma of a fluorine-based gas, and the semiconductor wafer 1 is sliced into semiconductor chips 1' along the boundary trenches 7.

Abstract translation: 在半导体晶片1上设置由芯片附着膜4和UV带5形成的膜层6作为掩模，形成在电路图案形成表面1a上形成的半导体元件2的边界沟槽7形成在膜 层6，从而使半导体晶片1的表面1c露出。 边界槽7中的半导体晶片1的露出面1c利用氟系气体的等离子体进行蚀刻，半导体晶片1沿着边界沟槽7切割成半导体芯片1'。