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    ELECTRICAL INTERCONNECT STRUCTURE FOR A SEMICONDUCTOR DEVICE AND AN ASSEMBLY USING THE SAME
    1.
    发明申请
    ELECTRICAL INTERCONNECT STRUCTURE FOR A SEMICONDUCTOR DEVICE AND AN ASSEMBLY USING THE SAME 审中-公开

    公开(公告)号：WO2021158339A1

    公开(公告)日：2021-08-12

    申请号：PCT/US2021/013114

    申请日：2021-01-12

    Applicant: MICRON TECHNOLOGY, INC.

    Inventor： KIRBY, Kyle K.

    IPC: H01L23/485 ,  H01L21/607

    Abstract: An electrical interconnect structure for a semiconductor device is provided herein. The electrical interconnect structure includes a conductive pillar (114) electrically coupled to a conductive contact (112) positioned on a emiconductor die (110) and a trace receiver (140) on a distal end of the pillar (114). The trace receiver (140) has a body (145) electrically coupled to the distal end, and may include a first leg(147a) projecting from a first side of the body (145) away from the distal end and a second leg (147b) projecting from a second side of the body (145) away from the distal end, such that the body (145), the first leg (147a), and the second leg (147b) together form a cavity. During assembly of the semiconductor device, the cavity is configured to at least partially surround a portion of a trace (122) positioned in an insulated substrate (120). To form the electrical connection, a solder material (142) may be disposed between the trace receiver (140) and the trace (122).

    FRONT END OF LINE INTERCONNECT STRUCTURES AND ASSOCIATED SYSTEMS AND METHODS
    3.
    发明申请
    FRONT END OF LINE INTERCONNECT STRUCTURES AND ASSOCIATED SYSTEMS AND METHODS 审中-公开

    公开(公告)号：WO2022046483A1

    公开(公告)日：2022-03-03

    申请号：PCT/US2021/046461

    申请日：2021-08-18

    Applicant: MICRON TECHNOLOGY, INC.

    Inventor： KIRBY, Kyle K. ,  PAREKH, Kunal R.

    IPC: H01L21/768

    Abstract: Systems and methods for a semiconductor device having a substrate material with a trench at a front side, a conformal dielectric material over at least a portion of the front side of the substrate material and in the trench, a fill dielectric material on the conformal dielectric material in the trench, and a conductive portion formed during front-end-of-line (FEOL) processing. The conductive portion may include an FEOL interconnect via extending through the fill dielectric material and at least a portion of the conformal dielectric material and having a front side portion defining a front side electrical connection extending beyond the front side of the semiconductor substrate material and a backside portion defining an active contact surface. The conductive portion may extend across at least a portion of the conformal dielectric material and the fill dielectric material and have a backside surface defining an active contact surface.

    COMBINATION-BONDED DIE PAIR PACKAGING AND ASSOCIATED METHODS
    4.
    发明申请
    COMBINATION-BONDED DIE PAIR PACKAGING AND ASSOCIATED METHODS 审中-公开

    公开(公告)号：WO2022066373A1

    公开(公告)日：2022-03-31

    申请号：PCT/US2021/048389

    申请日：2021-08-31

    Applicant: MICRON TECHNOLOGY, INC.

    Inventor： KIRBY, Kyle K. ,  STREET, Bret K.

    IPC: H01L25/065 ,  H01L21/98 ,  H01L21/60

    Abstract: Systems and methods for semiconductor devices having a substrate with bond pads, a die pair in a stacked configuration above the bond pads and having a first die having an oxide layer, a second die having an oxide layer attached to the first oxide layer, and conductive bonds electrically coupling the dies. Interconnects extend between the bond pads and the die pair, electrically coupling die pair to the substrate. The device may include a second die pair electrically coupled to: (1) the first die pair with secondary interconnects; and (2) the substrate with through-silicon vias extending through the first die pair. The top die of a die pair may be a thick die for use at the top of a pair stack. Pairs may be created by matching dies of a first silicon wafer to dies of a second silicon wafer, combination bonding the wafers, and dicing the die pairs.

    MULTI-HEIGHT INTERCONNECT STRUCTURES AND ASSOCIATED SYSTEMS AND METHODS
    5.
    发明申请
    MULTI-HEIGHT INTERCONNECT STRUCTURES AND ASSOCIATED SYSTEMS AND METHODS 审中-公开

    公开(公告)号：WO2021158340A1

    公开(公告)日：2021-08-12

    申请号：PCT/US2021/013117

    申请日：2021-01-12

    Applicant: MICRON TECHNOLOGY, INC.

    Inventor： KIRBY, Kyle K.

    IPC: H01L25/065 ,  H01L21/60

    Abstract: Systems and methods for multi-height interconnect structures for a semiconductor device are provided herein. The multi-height interconnect structure generally includes a primary level semiconductor die (120) having a primary conductive pillar (122) and a secondary conductive pillar (132), where the primary conductive pillar has a greater height than the secondary conductive pillar. The semiconductor device may further include a substrate (110) electrically coupled to the primary level semiconductor die through the primary conductive pillar and a secondary level semiconductor die (130) electrically coupled to the primary level semiconductor die through the secondary conductive pillar. The multi-height pillars may be formed using a single photoresist mask or multiple photoresist masks. In some configurations, the primary and secondary conductive pillars may be arranged on only the front-side of the dies and/or substrate.

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