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    MRAM DEVICE AND INTEGRATION TECHNIQUES COMPATIBLE WITH LOGIC INTEGRATION
    1.
    发明申请
    MRAM DEVICE AND INTEGRATION TECHNIQUES COMPATIBLE WITH LOGIC INTEGRATION 审中-公开
    MRAM设备和集成技术兼容逻辑集成

    公开(公告)号：WO2012019135A3

    公开(公告)日：2012-03-29

    申请号：PCT/US2011046811

    申请日：2011-08-05

    Applicant: QUALCOMM INC ,  LI XIA ,  ZHU XIAOCHUN ,  KANG SEUNG H

    Inventor： LI XIA ,  ZHU XIAOCHUN ,  KANG SEUNG H

    IPC: H01L27/22 ,  B82Y25/00 ,  H01L43/08 ,  H01L43/12

    CPC classification number: H01L43/12 ,  B82Y10/00 ,  G11C11/161 ,  H01L27/228 ,  H01L43/08

    Abstract: A semiconductor device includes a magnetic tunnel junction (MTJ) storage element configured to be disposed in a common interlayer metal dielectric (IMD) layer with a logic element. Cap layers separate the common IMD layer from a top and bottom IMD layer. Top and bottom electrodes are coupled to the MTJ storage element. Metal connections to the electrodes are formed in the top and bottom IMD layers respectively through vias in the separating cap layers. Alternatively, the separating cap layers are recessed and the bottom electrodes are embedded, such that direct contact to metal connections in the bottom IMD layer is established. Metal connections to the top electrode in the common IMD layer are enabled by isolating the metal connections from the MTJ storage elements with metal islands and isolating caps.

    Abstract translation: 一种半导体器件包括被配置为设置在具有逻辑元件的公共层间金属电介质（IMD）层中的磁性隧道结（MTJ）存储元件。 盖层将普通IMD层与顶部和底部IMD层分开。 顶部和底部电极连接到MTJ存储元件。 与电极的金属连接分别通过分离帽层中的通孔形成在顶部和底部IMD层中。 可选地，分离盖层凹入并且底部电极被嵌入，从而建立与底部IMD层中的金属连接的直接接触。 通过将金属连接与MTJ存储元件与金属岛和隔离帽隔离，可以实现与公共IMD层中的顶部电极的金属连接。

    MAGNETIC TUNNEL JUNCTION (MTJ) AND METHODS, AND MAGNETIC RANDOM ACCESS MEMORY (MRAM) EMPLOYING SAME
    2.
    发明申请
    MAGNETIC TUNNEL JUNCTION (MTJ) AND METHODS, AND MAGNETIC RANDOM ACCESS MEMORY (MRAM) EMPLOYING SAME 审中-公开
    磁性隧道结（MTJ）和方法以及使用其的磁性随机存取存储器（MRAM）

    公开(公告)号：WO2010120918A3

    公开(公告)日：2011-01-20

    申请号：PCT/US2010031080

    申请日：2010-04-14

    Applicant: QUALCOMM INC ,  ZHU XIAOCHUN ,  NOWAK MATTHEW ,  LI XIA ,  KANG SEUNG H

    Inventor： ZHU XIAOCHUN ,  NOWAK MATTHEW ,  LI XIA ,  KANG SEUNG H

    IPC: H01L27/115 ,  G11B5/39 ,  G11C11/15

    CPC classification number: H01L43/02 ,  G11C11/16 ,  G11C11/161 ,  G11C11/1659 ,  H01F10/3254 ,  H01F10/3272 ,  H01L27/228 ,  H01L43/08 ,  H01L43/12

    Abstract: Magnetic tunnel junctions (MTJs) and methods of forming same are disclosed. A pinned layer is disposed in the MTJ such that a free layer of the MTJ can couple to a drain of an access transistor when provided in a magnetic random access memory (MRAM) bitcell. This structure alters the write current flow direction to align the write current characteristics of the MTJ with write current supply capability of an MRAM bitcell employing the MTJ. As a result, more write current can be provided to switch the MTJ from a parallel (P) to anti-parallel (AP) state. An anti-ferromagnetic material (AFM) layer is provided on the pinned layer to fix pinned layer magnetization. To provide enough area for depositing the AFM layer to secure pinned layer magnetization, a pinned layer having a pinned layer surface area greater than a free layer surface area of the free layer is provided.

    Abstract translation: 公开了磁隧道结（MTJ）及其形成方法。 被钉扎层设置在MTJ中，使得当提供在磁随机存取存储器（MRAM）位单元中时，MTJ的自由层可以耦合到存取晶体管的漏极。 该结构改变写入电流流动方向，以使MTJ的写入电流特性与使用MTJ的MRAM位单元的写入电流供应能力对准。 结果，可以提供更多的写入电流以将MTJ从并行（P）切换到反并行（AP）状态。 在钉扎层上提供反铁磁材料（AFM）层以固定钉扎层的磁化强度。 为了提供足够的用于沉积AFM层以确保钉扎层磁化的区域，提供了具有大于自由层的自由层表面积的钉扎层表面积的钉扎层。

    FABRICATION AND INTEGRATION OF DEVICES WITH TOP AND BOTTOM ELECTRODES INCLUDING MAGNETIC TUNNEL JUNCTIONS
    5.
    发明申请
    FABRICATION AND INTEGRATION OF DEVICES WITH TOP AND BOTTOM ELECTRODES INCLUDING MAGNETIC TUNNEL JUNCTIONS 审中-公开
    具有包括磁性隧道结的顶部和底部电极的装置的制造和集成

    公开(公告)号：WO2011066579A3

    公开(公告)日：2011-07-21

    申请号：PCT/US2010058445

    申请日：2010-11-30

    Applicant: QUALCOMM INC ,  LI XIA ,  KANG SEUNG H

    Inventor： LI XIA ,  KANG SEUNG H

    IPC: H01L43/12 ,  G11C11/16 ,  H01F10/32 ,  H01L27/22

    CPC classification number: H01L43/12 ,  B82Y25/00 ,  B82Y40/00 ,  G11C11/161 ,  H01F10/3254 ,  H01F41/307 ,  H01L27/222 ,  H01L43/08

    Abstract: Disclosed is an electronic device manufacturing process including depositing a bottom electrode layer (711). Then an electronic device (721) is fabricated on the bottom electrode layer. Patterning of the bottom electrode layer is performed after fabricating the electronic device and in a separate process from patterning a top electrode. A first dielectric layer (740) is then deposited on the electronic device and the bottom electrode layer followed by a top electrode layer (751). The top electrode is then patterned in a separate process from the bottom electrode. Separately patterning the top and bottom electrodes improves yields by reducing voids in the dielectric material between electronic devices. One electronic device the manufacturing process is well -suited for is magnetic tunnel junctions (MTJs).

    Abstract translation: 公开了一种电子器件制造方法，包括沉积底部电极层（711）。 然后在底部电极层上制造电子器件（721）。 底部电极层的图案化是在制造电子器件之后并且在单独的工艺中对图案化顶部电极进行的。 然后，第一电介质层（740）沉积在电子器件上，底部电极层后面是顶部电极层（751）。 然后在与底部电极分离的工艺中对顶部电极进行图案化。 单独图案化顶部和底部电极通过减少电子器件之间的电介质材料中的空隙来提高产率。 磁性隧道结（MTJ）是制造工艺很好的一种电子器件。

    MAGNETIC TUNNEL JUNCTION DEVICE AND FABRICATION
    7.
    发明申请
    MAGNETIC TUNNEL JUNCTION DEVICE AND FABRICATION 审中-公开
    磁性隧道连接装置和制造

    公开(公告)号：WO2011032187A3

    公开(公告)日：2011-09-15

    申请号：PCT/US2010056249

    申请日：2010-11-10

    Applicant: QUALCOMM INC ,  LI XIA ,  KANG SEUNG H

    Inventor： LI XIA ,  KANG SEUNG H

    IPC: H01L43/12 ,  H01L27/22

    CPC classification number: H01L43/02 ,  G11C11/16 ,  G11C11/161 ,  H01L43/08 ,  H01L43/12

    Abstract: A magnetic tunnel junction, or MTJ, device and fabrication method is disclosed. In a particular embodiment, a method of forming an MTJ device includes forming a top electrode layer (120) over an MTJ structure (106). The top electrode layer includes a first nitrified metal.

    Abstract translation: 公开了磁性隧道结或MTJ，器件和制造方法。 在特定实施例中，形成MTJ器件的方法包括在MTJ结构（106）上形成顶部电极层（120）。 顶部电极层包括第一硝化金属。

    MAGNETIC TUNNEL JUNCTION DEVICE
    8.
    发明申请
    MAGNETIC TUNNEL JUNCTION DEVICE 审中-公开
    磁铁隧道连接装置

    公开(公告)号：WO2011072058A2

    公开(公告)日：2011-06-16

    申请号：PCT/US2010059541

    申请日：2010-12-08

    Applicant: QUALCOMM INC ,  ZHU XIAOCHUN ,  KANG SEUNG H ,  LI XIA ,  LEE KANGHO

    Inventor： ZHU XIAOCHUN ,  KANG SEUNG H ,  LI XIA ,  LEE KANGHO

    IPC: H01L43/08

    CPC classification number: H01L43/02 ,  H01L27/222 ,  H01L43/08 ,  H01L43/10 ,  H01L43/12

    Abstract: A system and method of manufacturing and using a magnetic tunnel junction device is disclosed. In a particular embodiment, a magnetic tunnel junction device includes a first free layer and second free layer. The magnetic tunnel junction also includes a spin torque enhancement layer. The magnetic tunnel junction device further includes a spacer layer between the first and second free layers that includes a material and has a thickness that substantially inhibits exchange coupling between the first and second free layers. The first and second free layers are magneto-statically coupled.

    Abstract translation: 公开了制造和使用磁性隧道结装置的系统和方法。 在特定实施例中，磁性隧道结装置包括第一自由层和第二自由层。 磁隧道结还包括自旋转矩增强层。 磁性隧道结器件还包括位于第一和第二自由层之间的间隔层，其包括材料并且具有基本上抑制第一和第二自由层之间的交换耦合的厚度。 第一和第二自由层是磁静态耦合的。

    PREDICTIVE MODELING OF INTERCONNECT MODULES FOR ADVANCED ON-CHIP INTERCONNECT TECHNOLOGY
    9.
    发明申请
    PREDICTIVE MODELING OF INTERCONNECT MODULES FOR ADVANCED ON-CHIP INTERCONNECT TECHNOLOGY 审中-公开
    互连模块用于先进片上互联技术的预测建模

    公开(公告)号：WO2010011448A3

    公开(公告)日：2010-04-01

    申请号：PCT/US2009047668

    申请日：2009-06-17

    Applicant: QUALCOMM INC ,  LI XIA ,  ZHAO WEI ,  CAO YU ,  GU SHIQUN ,  KANG SEUNG H ,  NOWAK MATTHEW

    Inventor： LI XIA ,  ZHAO WEI ,  CAO YU ,  GU SHIQUN ,  KANG SEUNG H ,  NOWAK MATTHEW

    IPC: G06F17/50

    CPC classification number: G06F17/5036

    Abstract: A computer program product estimates performance of an interconnect structure of a semiconductor integrated circuit (IC). The program product includes code executing on a computer to calculate at least one electrical characteristic of the interconnect structure based on input data accounting for multiple layers of the interconnect structure. The electrical characteristics can be capacitance, resistance, and/or inductance. The capacitance may be based upon multiple components, including a fringe capacitance component, a terminal capacitance component, and a coupling capacitance component.

    Abstract translation: 计算机程序产品估计半导体集成电路（IC）的互连结构的性能。 该程序产品包括在计算机上执行的代码，用于基于考虑互连结构的多个层的输入数据来计算互连结构的至少一个电特性。 电特性可以是电容，电阻和/或电感。 电容可以基于多个部件，包括边缘电容部件，端子电容部件和耦合电容部件。

    REDUCING SOURCE LOADING EFFECT IN SPIN TORQUE TRANSFER MAGNETORESITIVE RANDOM ACCESS MEMORY (STT-MRAM)
    10.
    发明申请
    REDUCING SOURCE LOADING EFFECT IN SPIN TORQUE TRANSFER MAGNETORESITIVE RANDOM ACCESS MEMORY (STT-MRAM) 审中-公开
    减少转子转子磁链随机存取存储器（STT-MRAM）中的源装载效应

    公开(公告)号：WO2010101860A3

    公开(公告)日：2010-11-11

    申请号：PCT/US2010025834

    申请日：2010-03-02

    Applicant: QUALCOMM INC ,  LEE KANGHO ,  KANG SEUNG H ,  ZHU XIAOCHUN

    Inventor： LEE KANGHO ,  KANG SEUNG H ,  ZHU XIAOCHUN

    IPC: G11C11/16

    CPC classification number: H01L43/08 ,  G06F17/5068 ,  G11C11/16 ,  G11C11/161 ,  G11C11/1675 ,  H01L43/02 ,  H01L43/12

    Abstract: Systems and methods to reduce source loading effects in STT-MRAM are disclosed. In a particular embodiment, a method includes determining a switching current ratio of a magnetic tunnel junction (MTJ) structure that enables stable operation of a memory cell. The memory cell includes the MTJ structure serially coupled to an access transistor. The method also includes modifying an offset magnetic field that is incident to a free layer of the MTJ structure. The modified offset magnetic field causes the MTJ structure to exhibit the switching current ratio.

    Abstract translation: 公开了减少STT-MRAM中的源负载效应的系统和方法。 在特定实施例中，一种方法包括确定使得能够稳定地操作存储器单元的磁性隧道结（MTJ）结构的开关电流比。 存储单元包括串行耦合到存取晶体管的MTJ结构。 该方法还包括修改入射到MTJ结构的自由层的偏移磁场。 改进的偏移磁场使MTJ结构呈现开关电流比。

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