公开(公告)号：WO2016122776A1

公开(公告)日：2016-08-04

申请号：PCT/US2015/064521

申请日：2015-12-08

Applicant: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC

Inventor： SEDDON, Michael J. ,  CARNEY, Francis J.

IPC: H01L21/60 ,  H01L23/482 ,  H01L23/485 ,  H01L21/78 ,  H01L21/683

CPC classification number: H01L24/32 ,  H01L21/4825 ,  H01L21/6836 ,  H01L21/78 ,  H01L23/482 ,  H01L24/03 ,  H01L24/05 ,  H01L24/11 ,  H01L24/13 ,  H01L24/16 ,  H01L24/17 ,  H01L24/27 ,  H01L24/28 ,  H01L24/29 ,  H01L24/30 ,  H01L24/31 ,  H01L24/33 ,  H01L24/81 ,  H01L24/83 ,  H01L24/94 ,  H01L2221/68327 ,  H01L2221/68381 ,  H01L2224/03416 ,  H01L2224/03418 ,  H01L2224/03444 ,  H01L2224/0345 ,  H01L2224/03452 ,  H01L2224/03462 ,  H01L2224/03464 ,  H01L2224/0347 ,  H01L2224/0348 ,  H01L2224/0401 ,  H01L2224/04026 ,  H01L2224/05075 ,  H01L2224/05082 ,  H01L2224/05083 ,  H01L2224/05147 ,  H01L2224/05155 ,  H01L2224/05166 ,  H01L2224/05171 ,  H01L2224/05639 ,  H01L2224/05647 ,  H01L2224/11462 ,  H01L2224/11464 ,  H01L2224/11849 ,  H01L2224/1308 ,  H01L2224/13111 ,  H01L2224/13139 ,  H01L2224/13147 ,  H01L2224/13155 ,  H01L2224/13166 ,  H01L2224/13171 ,  H01L2224/16227 ,  H01L2224/16503 ,  H01L2224/16507 ,  H01L2224/17106 ,  H01L2224/2908 ,  H01L2224/29082 ,  H01L2224/29083 ,  H01L2224/29111 ,  H01L2224/29139 ,  H01L2224/29147 ,  H01L2224/29155 ,  H01L2224/29166 ,  H01L2224/29171 ,  H01L2224/29565 ,  H01L2224/29582 ,  H01L2224/29655 ,  H01L2224/29666 ,  H01L2224/3003 ,  H01L2224/30505 ,  H01L2224/32225 ,  H01L2224/32245 ,  H01L2224/32503 ,  H01L2224/81439 ,  H01L2224/8181 ,  H01L2224/81815 ,  H01L2224/81825 ,  H01L2224/83439 ,  H01L2224/8381 ,  H01L2224/83815 ,  H01L2224/83825 ,  H01L2224/8481 ,  H01L2224/8581 ,  H01L2224/8681 ,  H01L2224/94 ,  H01L2924/00015 ,  H01L2924/01327 ,  H01L2924/10162 ,  H01L2924/12041 ,  H01L2224/03 ,  H01L2224/27 ,  H01L2924/00014 ,  H01L2924/00012 ,  H01L2924/01074 ,  H01L2924/01024 ,  H01L2924/20642 ,  H01L2224/48

Abstract: Methods of forming a semiconductor package (2, 12) are provided. Implementations include forming on a die backside (16) an intermediate metal layer (26) having multiple sublayers (40-46), each including a metal selected from the group consisting of titanium, nickel, copper, silver, and combinations thereof. A tin layer (48) is deposited onto the intermediate metal layer (26) and is then reflowed with a silver layer (52) of a substrate (50) to form an intermetallic layer (56) having a melting temperature above 260 degrees Celsius and including an intermetallic consisting of silver and tin and/or an intermetallic consisting of copper and tin. Another method of forming a semiconductor package includes forming a bump (22) on each of a plurality of exposed pads (20) of a top side (18) of a die (14), each exposed pad (20) surrounded by a passivation layer (24), each bump (22) including an intermediate metal layer (36) as described above and a tin layer (48) coupled to the intermediate metal layer (36), the tin layer (48) being then reflowed with a silver layer (52) of a substrate (50) to form an intermetallic layer (64), as described above.

Abstract translation: 提供形成半导体封装（2,12）的方法。 实施方案包括在模具背面（16）上形成具有多个子层（40-46）的中间金属层（26），每个子层包括选自钛，镍，铜，银及其组合的金属。 将锡层（48）沉积在中间金属层（26）上，然后用衬底（50）的银层（52）回流以形成熔点高于260摄氏度的金属间层（56），并且 包括由银和锡组成的金属间化合物和/或由铜和锡组成的金属间化合物。 形成半导体封装的另一种方法包括在裸片（14）的顶侧（18）的多个裸露焊盘（20）的每一个上形成凸块（22），每个裸露焊盘（20）被钝化层包围 （24）中，每个凸起（22）包括如上所述的中间金属层（36）和耦合到中间金属层（36）的锡层（48），然后锡层（48）用银层 （52），以形成金属间层（64），如上所述。