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    SELF-ALIGNED PROCESS
    1.
    发明申请
    SELF-ALIGNED PROCESS 审中-公开
    自对准过程

    公开(公告)号：WO2016111811A1

    公开(公告)日：2016-07-14

    申请号：PCT/US2015/065719

    申请日：2015-12-15

    Applicant: APPLIED MATERIALS, INC

    Inventor： PANDIT, Mandar B. ,  WANG, Anchuan ,  INGLE, Nitin K.

    IPC: H01L21/68

    CPC classification number: H01J37/32412 ,  H01J37/32357 ,  H01L21/3065 ,  H01L21/31116 ,  H01L21/31155 ,  H01L21/76825 ,  H01L21/76897

    Abstract: Methods of forming self-aligned structures on patterned substrates are described. The methods may be used to form metal lines or vias without the use of a separate photolithography pattern definition operation. Self-aligned contacts may be produced regardless of the presence of spacer elements. The methods include directionally ion-implanting a gapfill portion of a gapfill silicon oxide layer to implant into the gapfill portion without substantially ion-implanting the remainder of the gapfill silicon oxide layer (the sidewalls). Subsequently, a remote plasma is formed using a fluorine-containing precursor to etch the patterned substrate such that the gapfill portions of silicon oxide are selectively etched relative to other exposed portions exposed parallel to the ion implantation direction. Without ion implantation, the etch operation would be isotropic owing to the remote nature of the plasma excitation during the etch process.

    Abstract translation: 描述了在图案化衬底上形成自对准结构的方法。 该方法可用于形成金属线或通孔而不使用单独的光刻图案定义操作。 可以产生自对准的触点，而不管间隔元件的存在。 所述方法包括定向地离子注入间隙填充氧化硅层的间隙填充部分以注入到间隙填充部分中，而基本上不离子注入间隙填充氧化硅层（侧壁）的剩余部分。 随后，使用含氟前体形成远程等离子体以蚀刻图案化衬底，使得相对于平行于离子注入方向暴露的其它暴露部分选择性地蚀刻氧化硅的间隙填充部分。 在没有离子注入的情况下，蚀刻操作将是各向同性的，这是由于在蚀刻过程期间等离子体激发的远端特性。

    SELECTIVE ATOMIC LAYER DEPOSITION PROCESS UTILIZING PATTERNED SELF ASSEMBLED MONOLAYERS FOR 3D STRUCTURE SEMICONDUCTOR APPLICATIONS
    2.
    发明申请
    SELECTIVE ATOMIC LAYER DEPOSITION PROCESS UTILIZING PATTERNED SELF ASSEMBLED MONOLAYERS FOR 3D STRUCTURE SEMICONDUCTOR APPLICATIONS 审中-公开
    选择性原子层沉积工艺利用图形自组装单层3D结构半导体应用

    公开(公告)号：WO2015156912A1

    公开(公告)日：2015-10-15

    申请号：PCT/US2015/017078

    申请日：2015-02-23

    Applicant: APPLIED MATERIALS, INC.

    Inventor： NEMANI, Srinivas D. ,  YIEH, Ellie Y. ,  GODET, Ludovic ,  FAN, Yin

    IPC: H01L21/336 ,  H01L21/205

    CPC classification number: H01L21/02304 ,  H01J37/32357 ,  H01J37/32403 ,  H01J37/32422 ,  H01L21/0228 ,  H01L21/02321 ,  H01L21/0234 ,  H01L21/31155 ,  H01L29/66795 ,  H01L29/66803

    Abstract: Methods for forming fin structure with desired materials formed on different locations of the fin structure using a selective deposition process for three dimensional (3D) stacking of fin field effect transistor (FinFET) for semiconductor chips are provided. In one embodiment, a method of forming a structure with desired materials on a substrate includes forming a patterned self-assembled monolayer on a circumference of a structure formed on a substrate, wherein the patterned self-assembled monolayer includes a treated layer formed among a self-assembled monolayer, and performing an atomic layer deposition process to form a material layer predominantly on the self-assembled monolayer from the patterned self-assembled monolayer.

    Abstract translation: 提供了使用用于半导体芯片的鳍状场效应晶体管（FinFET）的三维（3D）堆叠的选择性沉积工艺在翅片结构的不同位置形成所需材料的翅片结构的方法。 在一个实施例中，在衬底上形成具有期望材料的结构的方法包括在形成在衬底上的结构的圆周上形成图案化的自组装单层，其中所述图案化的自组装单层包括在自身中形成的处理层 并且执行原子层沉积工艺，以从图案化的自组装单层形成主要在自组装单层上的材料层。

    DOPING OF DIELECTRIC LAYERS
    3.
    发明申请
    DOPING OF DIELECTRIC LAYERS 审中-公开
    电介质层的掺杂

    公开(公告)号：WO2013085684A1

    公开(公告)日：2013-06-13

    申请号：PCT/US2012/065086

    申请日：2012-11-14

    Applicant: APPLIED MATERIALS, INC.

    Inventor： UNDERWOOD, Brian S. ,  INGLE, Nitin K. ,  MALLICK, Abhijit Basu

    IPC: H01L21/3115 ,  H01L21/318

    CPC classification number: H01L21/02356 ,  H01L21/02167 ,  H01L21/02211 ,  H01L21/02222 ,  H01L21/02274 ,  H01L21/02321 ,  H01L21/0234 ,  H01L21/31111 ,  H01L21/31155

    Abstract: Methods are described for forming and treating a flowable silicon-carbon-and-nitrogen-containing layer on a semiconductor substrate. The silicon and carbon constituents may come from a silicon-and-carbon-containing precursor while the nitrogen may come from a nitrogen-containing precursor that has been activated to speed the reaction of the nitrogen with the silicon-and-carbon-containing precursor at lower deposition temperatures. The initially-flowable silicon-carbon-and-nitrogen-containing layer is ion implanted to increase etch tolerance, prevent shrinkage, adjust film tension and/or adjust electrical characteristics. Ion implantation may also remove components which enabled the flowability, but are no longer needed after deposition. Some treatments using ion implantation have been found to decrease the evolution of properties of the film upon exposure to atmosphere.

    Abstract translation: 描述了用于在半导体衬底上形成和处理可流动的含硅 - 碳和氮的层的方法。 硅和碳组分可以来自含硅和碳的前体，而氮可以来自已经被活化以加速氮与含硅和碳的前体的反应的含氮前体 较低的沉积温度。 初始可流动的含硅碳和氮的层被离子注入以增加蚀刻耐受性，防止收缩，调节膜张力和/或调节电特性。 离子注入还可以去除能够流动的组分，但是在沉积后不再需要它们。 已经发现使用离子注入的一些处理降低了暴露于大气中的膜的性质的演变。

    DUAL STRESS DEVICE AND METHOD
    7.
    发明申请
    DUAL STRESS DEVICE AND METHOD 审中-公开
    双重应力装置和方法

    公开(公告)号：WO2008064227A3

    公开(公告)日：2008-09-18

    申请号：PCT/US2007085246

    申请日：2007-11-20

    Applicant: IBM ,  ANDERSON BRENT A ,  BRYANT ANDRES ,  NOWAK EDWARD J

    Inventor： ANDERSON BRENT A ,  BRYANT ANDRES ,  NOWAK EDWARD J

    IPC: H01L21/8238

    CPC classification number: H01L29/785 ,  H01L21/31155 ,  H01L21/76283 ,  H01L21/823807 ,  H01L21/823821 ,  H01L21/823878 ,  H01L27/1203 ,  H01L29/1037 ,  H01L29/66621 ,  H01L29/66795 ,  H01L29/7843 ,  H01L29/7846 ,  H01L29/7849

    Abstract: A semiconductor device (80,85) including semiconductor material (35,40) having a bend and a trench feature formed at the bend, and a gate structure (45,50) at least partially disposed in the trench feature. A method of fabricating a semiconductor structure including forming a semiconductor material with a trench feature over a layer, forming a gate structure at least partially in the trench feature, and bending the semiconductor material such that stress is induced in the semiconductor material in an inversion channel region of the gate structure.

    Abstract translation: 一种包括半导体材料（35,40）的半导体器件（80,85），所述半导体材料具有在所述弯曲处形成的弯曲部和沟槽特征以及至少部分地设置在所述沟槽特征中的栅极结构（45,50）。 一种制造半导体结构的方法，包括：在层上形成具有沟槽特征的半导体材料;至少部分地在沟槽特征中形成栅极结构;以及弯曲半导体材料，使得在半导体材料中的反转沟道 栅极结构的区域。

    METHOD AND APPARATUS FOR FABRICATING A HIGH DIELECTRIC CONSTANT TRANSISTOR GATE USING A LOW ENERGY PLASMA SYSTEM
    9.
    发明申请
    METHOD AND APPARATUS FOR FABRICATING A HIGH DIELECTRIC CONSTANT TRANSISTOR GATE USING A LOW ENERGY PLASMA SYSTEM 审中-公开
    使用低能量等离子体系统制造高介电常数晶体闸门的方法和装置

    公开(公告)号：WO2007106660A2

    公开(公告)日：2007-09-20

    申请号：PCT/US2007062841

    申请日：2007-02-27

    Applicant: APPLIED MATERIALS INC ,  CHUA THAI CHENG ,  HUNG STEVEN ,  LIU PATRICIA M ,  SATO TATSUYA ,  PATERSON ALEX M ,  TODOROV VALENTIN ,  HOLLAND JOHN P

    Inventor： CHUA THAI CHENG ,  HUNG STEVEN ,  LIU PATRICIA M ,  SATO TATSUYA ,  PATERSON ALEX M ,  TODOROV VALENTIN ,  HOLLAND JOHN P

    IPC: H01L21/31

    CPC classification number: H01L21/31155 ,  H01J37/32082 ,  H01J37/34 ,  H01L21/28185 ,  H01L21/28202 ,  H01L21/3144 ,  H01L21/316 ,  H01L21/31683 ,  H01L29/517

    Abstract: The present invention generally provides methods and apparatuses that are adapted to form a high quality dielectric gate layer on a substrate. Embodiments contemplate a method wherein a metal plasma treatment process is used in lieu of a standard nitridization process to form a high dielectric constant layer on a substrate. Embodiments further contemplate an apparatus adapted to "implant" metal ions of relatively low energy in order to reduce ion bombardment damage to the gate dielectric layer, such as a silicon dioxide layer and to avoid incorporation of the metal atoms into the underlying silicon. In general, the process includes the steps of forming a high-k dielectric and then treating the deposited material to form a good interface between the gate electrode and the high-k dielectric material. Embodiments also provide a cluster tool that is adapted to form a high-k dielectric material, terminate the surface of the high-k dielectric material, perform desirable post treatment steps, and form a gate layers.

    Abstract translation: 本发明通常提供适于在衬底上形成高质量电介质栅极层的方法和装置。 实施例考虑了一种方法，其中使用金属等离子体处理工艺代替标准氮化工艺以在衬底上形成高介电常数层。 实施例进一步考虑了一种适于“植入”相对较低能量的金属离子的设备，以便减少对诸如二氧化硅层的栅极介电层的离子轰击损伤，并避免将金属原子引入到下面的硅中。 通常，该方法包括以下步骤：形成高k电介质，然后处理沉积的材料以在栅电极和高k电介质材料之间形成良好的界面。 实施例还提供了一种适于形成高k电介质材料，终止高k电介质材料的表面，执行理想的后处理步骤并形成栅极层的簇工具。

    MULTIPLE LOW AND HIGH K GATE OXIDES ON SINGLE GATE FOR LOWER MILLER CAPACITANCE AND IMPROVED DRIVE CURRENT
    10.
    发明申请
    MULTIPLE LOW AND HIGH K GATE OXIDES ON SINGLE GATE FOR LOWER MILLER CAPACITANCE AND IMPROVED DRIVE CURRENT 审中-公开
    在单闸门上多个低K和高K门氧化物用于较低的电容和改进的驱动电流

    公开(公告)号：WO2007038237A3

    公开(公告)日：2007-07-26

    申请号：PCT/US2006036916

    申请日：2006-09-22

    Applicant: IBM ,  CHIDAMBARRAO DURESETI ,  DOKUMACI OMER ,  GLUSCHENKOV OLEG ,  BELYANSKY MICHAEL

    Inventor： CHIDAMBARRAO DURESETI ,  DOKUMACI OMER ,  GLUSCHENKOV OLEG ,  BELYANSKY MICHAEL

    IPC: H01L21/28 ,  H01L29/40

    CPC classification number: H01L29/512 ,  H01L21/26586 ,  H01L21/31155 ,  H01L29/517 ,  H01L29/66545 ,  H01L29/66553 ,  H01L29/66583

    Abstract: The present invention provides a semiconductor structure having at least one CMOS device in which the Miller capacitances, i-e., overlap capacitances, are reduced and the drive current is improved. The inventive structure includes a semiconductor substrate having at least one overlaying gate conductor, each of the at least one overlaying gate conductors has vertical edges; a first gate oxide located beneath the at least one overlaying gate conductor, the first gate oxide not extending beyond the vertical edges of the at least overlaying gate conductor; and a second gate oxide located beneath at least a portion of the at one overlaying gate conductor. In accordance with the present invention, the first gate oxide and the second gate oxide are selected from high k oxide-containing materials and low k oxide-containing materials, and the first gate oxide is higher k than the second gate oxide or vice-versa.

    Abstract translation: 本发明提供一种半导体结构，其具有至少一个CMOS器件，其中米勒电容，即重叠电容，并且驱动电流得到改善。 本发明的结构包括具有至少一个覆盖栅极导体的半导体衬底，所述至少一个覆盖栅极导体中的每一个具有垂直边缘; 位于所述至少一个覆盖栅极导体下方的第一栅极氧化物，所述第一栅极氧化物不延伸超过所述至少覆盖栅极导体的垂直边缘; 以及位于一个重叠栅极导体的至少一部分下方的第二栅极氧化物。 根据本发明，第一栅极氧化物和第二栅极氧化物选自含高K氧化物的材料和低K氧化物的材料，并且第一栅极氧化物比第二栅极氧化物高k，反之亦然 。

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