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公开(公告)号:WO2007124146A8
公开(公告)日:2008-12-18
申请号:PCT/US2007009819
申请日:2007-04-19
Applicant: DYNAMIC DETAILS INC , KUMAR RAJ , DREYER MONTE , TAYLOR MICHAEL J
Inventor: KUMAR RAJ , DREYER MONTE , TAYLOR MICHAEL J
CPC classification number: H05K3/4623 , H05K3/205 , H05K3/386 , H05K3/4069 , H05K3/423 , H05K3/4614 , H05K3/4617 , H05K3/462 , H05K2201/0355 , H05K2201/0394 , H05K2201/09309 , H05K2201/096 , H05K2203/0191 , H05K2203/0271 , H05K2203/0502 , H05K2203/061 , H05K2203/0733 , H05K2203/107 , H05K2203/1461 , H05K2203/1536 , H05K2203/304 , Y10T29/49126 , Y10T29/49155 , Y10T29/49165
Abstract: Printed circuit boards having circuit layers laminated with stacked (or staggered) micro via(s) and methods of manufacturing the same. Aspects of embodiments of the present invention are directed to a printed circuit board with Z-axis interconnect(s) or micro via(s) that can eliminate a need for plating micro vias and/or eliminate a need for planarizing plated bumps of a surface, that can be fabricated with one or two lamination cycles, and/or that can have carrier-to-carrier (or substrate-to-substrate) attachments with conductive vias, each filled with a conductive material (e.g., with a conductive paste) in the Z-axis. In one embodiment, a printed circuit board having a plurality of circuit layers with at least one z-axis interconnect can be fabricated using a single lamination cycle.
Abstract translation: 具有层叠(或交错)微通孔的电路层的印刷电路板及其制造方法。 本发明的实施例的方面涉及具有Z轴互连或微通孔的印刷电路板,所述印刷电路板可以消除对微通孔镀敷的需要和/或消除平面化表面的镀凸块的需要 ,其可以用一个或两个层压循环制造,和/或可以具有导电通孔的载体与载体(或衬底与衬底)附接件,每个导电通孔填充有导电材料(例如,用导电浆料) 在Z轴上。 在一个实施例中,具有多个具有至少一个z轴互连的电路层的印刷电路板可以使用单个层压周期来制造。
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公开(公告)号:WO2008139612A1
公开(公告)日:2008-11-20
申请号:PCT/JP2007/059888
申请日:2007-05-14
Applicant: イビデン株式会社
IPC: H05K3/46
CPC classification number: H05K3/4691 , H05K3/0052 , H05K3/429 , H05K3/4602 , H05K3/4652 , H05K2201/0187 , H05K2201/0191 , H05K2201/0209 , H05K2201/09536 , H05K2201/096 , H05K2203/1536
Abstract: 配線基板(19)は、第1基板(1)と、第1基板(1)より実装面積が小さい第2基板(2)と、第1基板(1)と第2基板(2)との間に設けられているベース基板(3)と、を積層して構成される。配線基板(19)は、第1基板(1)と第2基板(2)の少なくともいずれか一つに設けられたヴィア(44)を有する。配線基板(19)は、第1基板(1)と第2基板(2)との間に層間溝部(11)を有し、層間溝部(11)には、気体、液体及び固体の少なくともいずれか一つが充填されていることも可能である。
Abstract translation: 布线板(19)通过堆叠第一板(1),具有小于第一板(1)的安装面积的第二板(2)和设置在第一板(1)之间的基板 (1)和第二板(2)。 布线板(19)具有形成在第一板(1)和第二板(2)中的至少一个上的通孔(44)。 布线板(19)在第一板(1)和第二板(2)之间具有层间沟槽部(11)。 气体,液体和固体中的至少一种可能填充在层间沟槽部分(11)中。
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3.
公开(公告)号:WO2007124146A3
公开(公告)日:2008-10-16
申请号:PCT/US2007009819
申请日:2007-04-19
Applicant: DYNAMIC DETAILS INC , KUMAR RAJ , DREYER MONTE , TAYLOR MICHAEL J
Inventor: KUMAR RAJ , DREYER MONTE , TAYLOR MICHAEL J
CPC classification number: H05K3/4623 , H05K3/205 , H05K3/386 , H05K3/4069 , H05K3/423 , H05K3/4614 , H05K3/4617 , H05K3/462 , H05K2201/0355 , H05K2201/0394 , H05K2201/09309 , H05K2201/096 , H05K2203/0191 , H05K2203/0271 , H05K2203/0502 , H05K2203/061 , H05K2203/0733 , H05K2203/107 , H05K2203/1461 , H05K2203/1536 , H05K2203/304 , Y10T29/49126 , Y10T29/49155 , Y10T29/49165
Abstract: Printed circuit boards having circuit layers laminated with stacked (or staggered) micro via(s) and methods of manufacturing the same. Aspects of embodiments of the present invention are directed to a printed circuit board with Z-axis interconnect(s) or micro via(s) that can eliminate a need for plating micro vias and/or eliminate a need for planarizing plated bumps of a surface, that can be fabricated with one or two lamination cycles, and/or that can have carrier-to-carrier (or substrate-to-substrate) attachments with conductive vias, each filled with a conductive material (e.g., with a conductive paste) in the Z-axis. In one embodiment, a printed circuit board having a plurality of circuit layers with at least one z-axis interconnect can be fabricated using a single lamination cycle.
Abstract translation: 具有层叠有(或交错)微通道的电路层的印刷电路板及其制造方法。 本发明的实施例的方面涉及具有Z轴互连或微通道的印刷电路板,其可以消除对电镀微通孔的需要和/或消除对平面化电镀凸块的需要 ,可以用一个或两个层压循环制造,和/或可以具有导电通孔的载流子到载体(或基底对基底)附件,每个填充有导电材料(例如,使用导电浆料) 在Z轴上。 在一个实施例中,可以使用单个层压循环来制造具有具有至少一个z轴互连的多个电路层的印刷电路板。
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4.
公开(公告)号:WO2007124146A2
公开(公告)日:2007-11-01
申请号:PCT/US2007/009819
申请日:2007-04-19
Applicant: DYNAMIC DETAILS, INC. , KUMAR, Raj , DREYER, Monte , TAYLOR, Michael, J.
Inventor: KUMAR, Raj , DREYER, Monte , TAYLOR, Michael, J.
IPC: H05K1/11
CPC classification number: H05K3/4623 , H05K3/205 , H05K3/386 , H05K3/4069 , H05K3/423 , H05K3/4614 , H05K3/4617 , H05K3/462 , H05K2201/0355 , H05K2201/0394 , H05K2201/09309 , H05K2201/096 , H05K2203/0191 , H05K2203/0271 , H05K2203/0502 , H05K2203/061 , H05K2203/0733 , H05K2203/107 , H05K2203/1461 , H05K2203/1536 , H05K2203/304 , Y10T29/49126 , Y10T29/49155 , Y10T29/49165
Abstract: Printed circuit boards having circuit layers laminated with stacked (or staggered) micro via(s) and methods of manufacturing the same. Aspects of embodiments of the present invention are directed to a printed circuit board with Z-axis interconnect(s) or micro via(s) that can eliminate a need for plating micro vias and/or eliminate a need for planarizing plated bumps of a surface, that can be fabricated with one or two lamination cycles, and/or that can have carrier-to-carrier (or substrate-to-substrate) attachments with conductive vias, each filled with a conductive material (e.g., with a conductive paste) in the Z-axis. In one embodiment, a printed circuit board having a plurality of circuit layers with at least one z-axis interconnect can be fabricated using a single lamination cycle.
Abstract translation: 具有层叠有(或交错)微通道的电路层的印刷电路板及其制造方法。 本发明的实施例的方面涉及具有Z轴互连或微通道的印刷电路板,其可以消除对电镀微通孔的需要和/或消除对平面化电镀凸块的需要 ,可以用一个或两个层压循环制造,和/或可以具有导电通孔的载流子到载体(或基底对基底)附件,每个填充有导电材料(例如,使用导电浆料) 在Z轴上。 在一个实施例中,可以使用单个层压循环来制造具有具有至少一个z轴互连的多个电路层的印刷电路板。
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5.
公开(公告)号:WO2004114730A2
公开(公告)日:2004-12-29
申请号:PCT/US2004/019090
申请日:2004-06-12
Applicant: OAK-MITSUI, INC.
Inventor: WEEKES, Michael , SIRCO, Anthony, J. , BLABER, John
IPC: H05K
CPC classification number: B32B15/017 , B32B15/08 , H05K3/025 , H05K2203/0152 , H05K2203/1536 , Y10T428/12354 , Y10T428/12493 , Y10T428/239
Abstract: A metal foil composite structure used for the construction of clad laminate and printed circuit wiring boards comprises first and second conductive metal foil layers having substantially the same width. Each of the layers has opposite lateral edges. A carrier layer is disposed between the first and second conductive metal layers. The carrier layer has a width less than the width of the first and second conductive metal layers, and forms a margin at each of the lateral edges. The first and second conductive layers are joined to each other only within the margins. Strength provided by the carrier enables thin conducting metal foils to be incorporated in clad laminates. Such foils, which may be as thin as 8 - 10 µm, are often too weak to be reliably selfsupporting. The provision of a supporting carrier layer enables the thin foils to be handled and bonded to a dielectric substrate in an efficient and economical manner. Defects in the resulting clad laminate, such as wrinking or creasing of the thin foil, are virtually eliminated. The composite foil structure is readily formed in continuous, indeterminate lengths.
Abstract translation: 用于覆盖层压板和印刷电路布线板的构造的金属箔复合结构包括具有基本上相同宽度的第一和第二导电金属箔层。 每个层具有相对的横向边缘。 载体层设置在第一和第二导电金属层之间。 载体层的宽度小于第一和第二导电金属层的宽度,并且在每个侧边缘处形成边缘。 第一和第二导电层仅在边缘内相互连接。 由载体提供的强度使得能够将薄导电金属箔并入包覆层压板中。 这样的箔可以是8-10μm,通常太弱而不能可靠地自支撑。 提供支撑载体层使得能够以有效和经济的方式将薄箔处理并结合到电介质基板。 实际上消除了所产生的覆盖层压板的缺陷,例如薄箔的起皱或褶皱。 复合箔结构容易形成为连续的,不确定的长度。
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公开(公告)号:WO03023823A2
公开(公告)日:2003-03-20
申请号:PCT/US0228628
申请日:2002-09-09
Applicant: IRVINE SENSORS CORP , YAMAGUCHI JAMES SATSUO , PEPE ANGEL ANTONIO , OZGUZ VOLKAN H , CAMIEN ANDREW NELSON
Inventor: YAMAGUCHI JAMES SATSUO , PEPE ANGEL ANTONIO , OZGUZ VOLKAN H , CAMIEN ANDREW NELSON
IPC: H01L23/373 , H01L25/065 , H01L25/10 , H05K3/00 , H05K3/40 , H01L
CPC classification number: H01L25/50 , H01L23/3735 , H01L23/3737 , H01L25/0652 , H01L25/105 , H01L2225/1023 , H01L2225/1064 , H01L2924/0002 , H05K3/0052 , H05K3/0097 , H05K3/403 , H05K2201/0129 , H05K2203/1105 , H05K2203/1536 , H05K2203/167 , H01L2924/00
Abstract: Each multilayer module (10) of a plurality of multilayer modules has a plurality of layers (20) wherein each layer has a substrate (22) therein. The plurality of multilayer modules (10) includes a first multilayer module (10) including a first layer (20) and a second multilayer (10) module including a second layer (20) each having a top side and bottom side. The first layer (20) and second layer (20) each includes a substrate (22), at least one electronic element (26), and a plurality of electrically-conductive traces (28). The plurality of multilayer modules (10) further includes a heat-separating layer (40) disposed between the top side of the first layer (20) and the bottom side of the second layer (20). The first multilayer module (10) is adhered to the second multilayer module (10) and the first multilayer module (10) can be detached from the second multilayer module (10) by applying heat to the heat-separating layer (40).
Abstract translation: 多个多层模块的每个多层模块(10)具有多个层(20),其中每层在其中具有衬底(22)。 多个多层模块(10)包括包括第一层(20)和第二多层(10)模块的第一多层模块(10),所述第二层模块包括第二层(20),每个层具有顶侧和底侧。 第一层(20)和第二层(20)各自包括基底(22),至少一个电子元件(26)和多个导电迹线(28)。 多个多层模块(10)还包括设置在第一层(20)的顶侧和第二层(20)的底侧之间的热分离层(40)。 第一多层模块(10)被粘附到第二多层模块(10),并且第一多层模块(10)可以通过向热分离层(40)施加热量而从第二多层模块(10)分离。
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7.
公开(公告)号:WO1997018695A1
公开(公告)日:1997-05-22
申请号:PCT/CH1996000394
申请日:1996-11-06
Applicant: DYCONEX PATENTE AG , SCHMIDT, Walter
Inventor: DYCONEX PATENTE AG
IPC: H05K03/46
CPC classification number: H05K3/4655 , H05K3/0097 , H05K3/025 , H05K3/4652 , H05K3/4676 , H05K2201/0195 , H05K2201/0355 , H05K2201/0358 , H05K2203/1536
Abstract: The invention relates to a process for making printed circuit boards from semi-finished foil products (F.2/6/6'/6") in which at least two semi-finished foil products (F.2/6/6'/6") are bonded together under pressure and temperature via at least two viscous insulating layers (2, 7) which are physically different from each other in that one insulating layer (7) does not melt to liquid form and acts as a spacer, the other insulating layer (2) melts to liquid form during bonding and acts as a bonding agent, a bonding semi-finished foil product (F.2/6/6'/6") with insulating layers (2, 7) is used therefor and spacing insulating layers (7) are applied to conductive layers (1) and bonding insulating layers (2) are applied to spacing insulating layers (7).
Abstract translation: 本发明涉及一种用于制造印刷电路板的从半成品箔制品(F.2 / 6/6的方法“/ 6),其中至少两个膜的半成品(F.2 / 6/6” / 6)一起压力和温度的至少两个下粘性 绝缘层(2,7)连接,其由绝缘体层物理上彼此不同(7)不会熔化连接并充当间隔装置期间流动,即(2)的其它绝缘体层中流动连接期间熔化并用作连接装置,为了这个目的 连接半成品箔制品使用具有绝缘层(F.6 / 6“/ 6)(2,7),并且该空间保持绝缘层(7)被施加到导电层(1)和施加(7)上空间保持绝缘层连接绝缘体层(2) 是。
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公开(公告)号:WO2014109357A1
公开(公告)日:2014-07-17
申请号:PCT/JP2014/050229
申请日:2014-01-09
Applicant: 日立化成株式会社
IPC: H05K3/46
CPC classification number: H05K3/4682 , H05K3/007 , H05K3/0097 , H05K3/025 , H05K3/427 , H05K2201/09509 , H05K2203/0152 , H05K2203/1536
Abstract: プリプレグAを挟んだ両側に、銅箔Aと銅箔Bとを有するピーラブル銅箔を配置し、さらに両側にプリプレグBと銅箔Cとを配置して積層し、支持材付き積層体を形成する工程(1)を有する配線基板の製造方法。また、プリプレグAを挟んだ両側に、銅箔Aと銅箔Bとを有するピーラブル銅箔を配置し、さらに両側にプリプレグBと銅箔Cとを配置して積層した支持材付き積層体。
Abstract translation: 一种布线板的制造方法,其特征在于,包括具有铜箔(A)和铜箔(B)的剥离性铜箔的工序(1),在预浸料坯(A)的两面配置 夹持预浸料坯(A)和预浸料坯(B)和铜箔(C),层压在每个可剥离铜箔的外侧,由此形成具有支撑材料的层压体。 将预浸料坯(A)夹在预浸料坯(A)的两侧,配置有具有支撑材料的层叠体,其中具有铜箔(A)和铜箔(B)的剥离铜箔, ,并且在每个可剥离铜箔的外侧上布置并层压预浸料坯(B)和铜箔(C)。
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公开(公告)号:WO2011093427A1
公开(公告)日:2011-08-04
申请号:PCT/JP2011/051706
申请日:2011-01-28
CPC classification number: B32B37/226 , B32B7/12 , B32B15/08 , B32B15/20 , B32B27/16 , B32B27/281 , B32B37/0015 , B32B37/025 , B32B2307/538 , B32B2307/546 , B32B2307/732 , B32B2309/02 , B32B2309/04 , B32B2309/105 , B32B2311/00 , B32B2457/08 , H05K3/022 , H05K2201/0141 , H05K2203/1536
Abstract: 絶縁フィルムと金属箔との層間密着性に優れて、接着強度にばらつきがなく、しわ等の外観不具合の発生を抑制しながら、工業的に生産性良く片面金属張積層体を製造することができる方法を提供する。 熱可塑性樹脂からなる接着面を有した絶縁性フィルム(A)に金属箔(B)が接着された片面金属張積層体を製造する方法であって、表裏面のいずれもが表面粗さ(Rz)2.0μm以下である離間フィルム(C)を用いて、一対の加圧ロール(r 1 、r 2 )間で(r 1 )/(B)/(A)/(C)/(A)/(B)/(r 2 )の順となるように、絶縁性フィルム(A)、金属箔(B)、及び離間フィルム(C)を重ねて熱圧着し、離間フィルム(C)から剥離して2つの片面金属張積層体を得る片面金属張積層体の製造方法である。
Abstract translation: 提供了一种用于工业制造具有一个镀金侧的层压体的高生产率方法。 所述方法导致绝缘膜和金属箔之间的优异的层间粘合性,粘合强度没有变化。 所提供的方法还抑制诸如皱纹的美学缺陷的形成。 制造其中金属箔(B)与具有包含热塑性树脂的粘合剂表面的绝缘膜(A)结合的层压体的方法使用分隔膜(C),其两侧具有表面 粗糙度(Rz)为2.0μm以下。 绝缘膜(A),金属箔(B)和分隔膜(C)以r1,B,A,C,A,B,r2的顺序层叠在一对加压辊(r1和r2)之间, 通过热压粘合。 然后可以将两个具有一个金属镀层的层叠体与分隔膜(C)分离。
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公开(公告)号:WO2009011025A1
公开(公告)日:2009-01-22
申请号:PCT/JP2007/064025
申请日:2007-07-13
Applicant: イビデン株式会社
IPC: H05K3/46
CPC classification number: H05K3/4691 , H05K1/0366 , H05K3/0035 , H05K3/0052 , H05K3/429 , H05K3/4602 , H05K3/4652 , H05K2201/0191 , H05K2201/0209 , H05K2201/091 , H05K2201/09563 , H05K2201/096 , H05K2201/09845 , H05K2201/09909 , H05K2203/1536
Abstract: 配線基板19は、第1基板1と、第1基板1より実装面積が小さい第2基板2と、第1基板1と第2基板2との間に設けられているベース基板3と、を積層して構成され、外周の少なくとも一部の厚みが、中央部よりも薄く形成される。ヴィア44が、第1基板1と第2基板2の少なくともいずれか一つに設けられている。ベース基板3は、第1基板1にのみ接合する部分の厚さが、第1基板1と第2基板2とに挟持された部分の厚さよりも小さい。
Abstract translation: 布线板(19)通过堆叠第一基板(1),具有比第一基板(1)更小的安装面积的第二基板(2)和设置在第一基板(1)之间的基底基板 )和第二基板(2)。 其边缘的至少一部分的厚度小于其中心部分的厚度。 通孔(44)设置在第一基板(1)和第二基板(2)中的至少一个中。 仅与基底基板(3)的第一基板(1)接合的部分的厚度小于夹在第一基板(1)和第二基板(2)之间的部分的厚度。
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