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    DUTY-CYCLE-EFFICIENT SRAM CELL TEST
    2.
    发明授权
    DUTY-CYCLE-EFFICIENT SRAM CELL TEST 有权
    - 关于向占空比的高效SRAM单元测试

    公开(公告)号：EP1415305B1

    公开(公告)日：2008-09-03

    申请号：EP02787139.1

    申请日：2002-07-11

    Applicant: International Business Machines Corporation ,  Compagnie IBM France

    Inventor： NELSON, Erik.A ,  PILO,Harold

    IPC: G11C29/00

    CPC classification number: G11C29/28 ,  G11C29/34

    Abstract: A method and structure for the invention includes an integrated memory structure having a built-in test portion. The integrated memory structure has memory cells, bitlines and wordlines connected to the memory cells, wordline decoders connected to a plurality of the wordlines, bitline restore devices connected to the bitlines for charging the bitlines during read and write operations, and a clock circuit connected to the wordlines. During a test mode the wordline decoders simultaneously select multiple wordlines that the bitline restore devices maintain in an active state and the clock circuit maintains the multiple wordlines and the bitline restore devices in an active state for a period in excess of a normal read cycle. The invention also includes transistors which are connected to the memory cells. The transistors include bitline contacts which are stressed during the test mode.

    Method for reading non-volatile memory cells
    3.
    发明公开
    Method for reading non-volatile memory cells 审中-公开
    Verfahren zum LesennichtflüchtigerSpeicherzellen

    公开(公告)号：EP1670001A2

    公开(公告)日：2006-06-14

    申请号：EP05111880.0

    申请日：2005-12-09

    Applicant: Saifun Semiconductors Ltd.

    Inventor： Maayan, Eduardo ,  Cohen, Guy ,  Eitan, Boaz

    IPC: G11C16/26 ,  G11C16/04

    CPC classification number: G11C29/28 ,  G11C16/04 ,  G11C16/0475 ,  G11C29/02 ,  G11C29/021 ,  G11C29/026 ,  G11C29/50 ,  G11C29/50004

    Abstract: A method includes changing a read reference level for reading a group of memory cells as a function of changes in a threshold voltage distribution of a different group of memory cells. The changing step includes determining a history read reference level for correct reading of at least one history cell (64), selecting a memory read reference level according to the first read reference level, and reading non-volatile memory array cells (62) associated with the at least one history cell (64) using the memory read reference level.

    Abstract translation: 一种方法包括根据不同组的存储器单元的阈值电压分布的变化来改变用于读取一组存储器单元的读取参考电平。 改变步骤包括确定用于正确读取至少一个历史单元（64）的历史读取参考水平，根据第一读取参考水平选择存储器读取参考水平，以及读取与...相关联的非易失性存储器阵列单元（62） 所述至少一个历史单元（64）使用所述存储器读取参考电平。

    Anordnung zum Prüfen der Funktionsfähigkeit von Speicherplätzen eines Schreib-Lese-Speichers
    8.
    发明授权
    Anordnung zum Prüfen der Funktionsfähigkeit von Speicherplätzen eines Schreib-Lese-Speichers 失效
    检查的随机存取存储器的存储位置的可操作性的安排。

    公开(公告)号：EP0443070B1

    公开(公告)日：1995-09-20

    申请号：EP90103503.0

    申请日：1990-02-23

    Applicant: SCHEIDT & BACHMANN GMBH

    Inventor： Ehl, Rolf Josef ,  Schürmans, Peter, Dipl.-Ing.

    IPC: G06F12/06 ,  G06F11/20

    CPC classification number: G11C29/28

    Abstract: The invention relates to an arrangement for verifying the correct functioning of memory locations of a read/write memory (4a and 4b) in a computer, the CPU (1) of which is connected to the read/write memory (4a and 4b) via a data and address bus (2, 3). To provide the possibility of a verification of the read/write memory (4a and 4b) of any complexity at any time and without time restriction independently of the process run and even during interrupt processing, a number of storage locations corresponding to the number of storage locations is made available in a physically separate read/write memory (4b and 4a) which is operated via the same data and address bus (2, 3) by the same CPU (1). These storage locations of the two read/write memories (4a and 4b) are selected by a common control logic (5) in such a manner that both storage areas can be used as separately addressable memories, of which one storage area is optionally used as working memory whilst the other storage area is subjected to a verification program. In this arrangement, the write operations of the continuously presented process data occur in parallel in both memory areas between the alternations of the two memory areas for work and test purposes following one another in time. However, read operations only occur from the memory area which is currently being used as working memory, until all data have been transferred from the memory area used in each case as working memory into the tested memory area by reading-out and writing-back the entire working memory volume with the aid of the CPU (1).

    Multibit semiconductor memory device
    9.
    发明公开
    Multibit semiconductor memory device 失效
    多位-Halbleiterspeicheranordnung。

    公开(公告)号：EP0655744A1

    公开(公告)日：1995-05-31

    申请号：EP94117211.6

    申请日：1994-10-31

    Applicant: NEC CORPORATION

    Inventor： Matsui, Yoshinori

    IPC: G11C29/00

    CPC classification number: G11C29/48 ,  G11C29/28

    Abstract: A multibit semiconductor memory device for inputting and outputting data in a parallel fashion in a unit of bits. The multibit memory has a memory cell array composed of mixed memory cells corresponding to different IO bits, data I/O terminals corresponding respectively to IO bits, an address terminal for inputting an address and internal data buses associated respectively with the IO bits and connected to the memory cell array. Further, the memory device has a test mode entry signal generator for generating a test mode entry signal indicative of entry into a test mode, a pseudo-address generator connected to the address terminal, for generating a pseudo-address in the test mode, and a connecting circuit responsive to the test mode entry signal for selecting one of the internal data buses depending on the pseudo-address and connecting the selected bus to predetermined one of the data I/O terminals.

    Abstract translation: 一种用于以比特为单位并行输入和输出数据的多位半导体存储器件。 多位存储器具有存储单元阵列，该存储单元阵列由对应于不同IO位的混合存储器单元，分别对应于IO位的数据I / O端子，用于输入地址的地址端子和分别与IO位相关联的内部数据总线组成 存储单元阵列。 此外，存储器件具有测试模式输入信号发生器，用于产生指示进入测试模式的测试模式输入信号，连接到地址终端的伪地址产生器，用于在测试模式中产生伪地址;以及 响应于测试模式输入信号的连接电路，用于根据伪地址选择一个内部数据总线，并将所选择的总线连接到数据I / O端子中的预定的一个。

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