公开(公告)号：EP1860417A3

公开(公告)日：2009-11-18

申请号：EP07008470.2

申请日：2007-04-26

Applicant: Sensirion Holding AG

Inventor： Sunier, Robert ,  Streiff, Matthias ,  Mayer, Felix ,  Bühler, Johannes

IPC: G01L19/00 ,  B81B7/02 ,  H01G7/00 ,  G01L9/12 ,  B81B5/00

CPC classification number: G01L9/0073 ,  B81B2201/0264 ,  B81C1/0023 ,  B81C1/00238 ,  B81C2201/019 ,  G01L9/0042 ,  H01L23/10 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A pressure sensor is manufactured by joining two wafers (1a, 14), the first wafer comprising CMOS circuitry (2) and the second being an SOI wafer. A recess is formed in the top material layer of the first wafer (1a), which is covered by the silicon layer (17) of the second wafer (14) to form a cavity (18). Part or all of the substrate (15) of the second wafer (14) is removed to forming a membrane from the silicon layer (17). Alternatively, the cavity can be formed in the second wafer (14). The second wafer (14) is electrically connected to the circuitry (2) on the first wafer (1a). This design allows to use standard CMOS processes for integrating circuitry on the first wafer (1a).

公开(公告)号：EP1663850B1

公开(公告)日：2009-09-16

申请号：EP04773454.6

申请日：2004-09-21

Applicant: Panasonic Electric Works Co., Ltd.

Inventor： OKA, Naomasa, c/o Panasonic Electric Works Co., Ltd ,  HARADA, Hiroshi, c/o Panasonic Electric Works Co.,Ltd. ,  OGIHARA, Jun, c/o Panasonic Electric Works Co., Ltd. ,  FUKSHIMA, Hiroshi, c/o Panasonic Electric Works Co., Ltd. ,  NOGE, Hiroshi, c/o Panasonic Electric Works Co.,Ltd. ,  SUZUKI, Yuji, c/o Panasonic Electric Works Co., Ltd. ,  KAWANO, Kiyohiko, c/o Panasonic Electric Works Co., Ltd. ,  YOSHIHARA, Takaaki, c/o Panasonic Electric Works Co., Ltd. ,  SUZUMURA, Masahiko, c/o Panasonic Electric Works Co.,Ltd.

IPC: B81B3/00 ,  G02B26/08 ,  B81C1/00

CPC classification number: G02B26/0816 ,  B81B3/0086 ,  B81B2201/033 ,  B81B2201/045 ,  B81C1/00484 ,  B81C2201/0109 ,  B81C2201/019 ,  G02B6/3516 ,  G02B6/3518 ,  G02B6/3546 ,  G02B6/355 ,  G02B6/357 ,  G02B6/3584 ,  H02N1/008

Abstract: A process for fabricating a micro-electro-mechanical system (MEMS) composed of fixed components fixedly supported on a lower substrate and movable components movably supported on the lower substrate. The process utilizes an upper substrate separate from the lower substrate. The upper substrate is selectively etched in its top layer to form therein a plurality of posts which project commonly from a bottom layer of the upper substrate. The posts include the fixed components to be fixed to the lower substrate and the movable components which are resiliently supported only to one or more of the fixed components to be movable relative to the fixed components. The lower substrate is formed in its top surface with at least one recess. The upper substrate is then bonded to the top of the lower substrate upside down in such a manner as to place the fixed components directly on the lower substrate and to place the movable components upwardly of the recess. Finally, the bottom layer of the upper substrate is removed to release the movable components from the bottom layer for floating the movable components above the recess and allowing them to move relative to the lower substrate, while keeping the fixed components fixed to the top of the lower substrate.

公开(公告)号：EP2084101A2

公开(公告)日：2009-08-05

申请号：EP07844369.4

申请日：2007-10-18

Applicant: Hewlett-packard Development Company, L. P.

Inventor： RAMAMOORTHI, Sriram ,  MILLIGAN, Donald J.

IPC: B81C1/00

CPC classification number: B81C1/00253 ,  B81B2201/0235 ,  B81B2203/051 ,  B81B2203/053 ,  B81C1/00142 ,  B81C3/004 ,  B81C2201/019 ,  B81C2203/058

Abstract: The present specification discloses an exemplary system and method for forming a micro-electro mechanical system (MEMS) transducer. According to one exemplary embodiment disclosed herein, the MEMS transducer is formed from two wafers and decouples the thickness of the proof mass and flexures, thereby allowing each to be independently designed. Additionally, the present exemplary system and method etches both sides of the wafer defining the flexures and the proof mass, allowing for optical alignment of the top and bottom wafers.

公开(公告)号：EP1345551B1

公开(公告)日：2009-04-01

申请号：EP01989783.4

申请日：2001-11-28

Applicant: CALIFORNIA INSTITUTE OF TECHNOLOGY

Inventor： UNGER, Marc, A. ,  CHOU, Hou-Pu ,  THORSEN, Todd, A. ,  SCHERER, Axel ,  QUAKE, Stephen, R. ,  LIU, Jian ,  ADAMS, Mark, L. ,  HANSEN, Carl, L.

IPC: A61F2/00

CPC classification number: B05D3/04 ,  B01J2219/00355 ,  B01J2219/00378 ,  B01J2219/00396 ,  B01J2219/00398 ,  B01J2219/00439 ,  B01J2219/005 ,  B01J2219/00527 ,  B01J2219/00605 ,  B01J2219/00612 ,  B01J2219/00621 ,  B01J2219/00659 ,  B01J2219/00707 ,  B01J2219/00722 ,  B01J2219/00725 ,  B01L3/502707 ,  B01L3/50273 ,  B01L3/502738 ,  B01L7/54 ,  B01L9/527 ,  B01L2200/025 ,  B01L2200/027 ,  B01L2200/0605 ,  B01L2200/10 ,  B01L2300/0681 ,  B01L2300/0861 ,  B01L2300/0887 ,  B01L2300/123 ,  B01L2300/14 ,  B01L2300/18 ,  B01L2400/046 ,  B01L2400/0481 ,  B01L2400/06 ,  B01L2400/0655 ,  B01L2400/0688 ,  B32B2037/1081 ,  B65B31/00 ,  B81B2201/036 ,  B81B2201/054 ,  B81C1/00119 ,  B81C2201/019 ,  C12Q1/6832 ,  C12Q1/6874 ,  C30B29/54 ,  F04B43/043 ,  F15C1/06 ,  F15C3/00 ,  F15C5/00 ,  F16K99/0001 ,  F16K99/0015 ,  F16K99/0046 ,  F16K99/0051 ,  F16K99/0059 ,  F16K2099/0074 ,  F16K2099/0076 ,  F16K2099/0078 ,  F16K2099/008 ,  F16K2099/0084 ,  F16K2099/0094 ,  Y10T137/0324 ,  Y10T137/0379 ,  Y10T137/0424 ,  Y10T137/206 ,  Y10T137/2082 ,  Y10T137/2164 ,  Y10T137/2169 ,  Y10T137/2174 ,  Y10T137/2202 ,  Y10T137/2224 ,  Y10T137/3084 ,  Y10T137/7837 ,  Y10T137/86027 ,  Y10T156/10 ,  Y10T428/24479 ,  Y10T428/24612 ,  C12Q2535/125

Abstract: A method of fabricating an elastomeric structure, comprising: forming a first elastomeric layer on top of a first micromachined mold, the first micromachined mold having a first raised protrusion which forms a first recess extending along a bottom surface of the first elastomeric layer; forming a second elastomeric layer on top of a second micromachined mold, the second micromachined mold having a second raised protrusion which forms a second recess extending along a bottom surface of the second elastomeric layer; bonding the bottom surface of the second elastomeric layer onto a top surface of the first elastomeric layer such that a control channel forms in the second recess between the first and second elastomeric layers; and positioning the first elastomeric layer on top of a planar substrate such that a flow channel forms in the first recess between the first elastomeric layer and the planar substrate.

公开(公告)号：EP1861926B1

公开(公告)日：2008-12-03

申请号：EP06737666.5

申请日：2006-03-09

Applicant: Honeywell International Inc.

Inventor： JAFRI, Ijaz, H. ,  MAGENDANZ, Galen, P. ,  KLEIN, Jonathan, L.

IPC: H03H9/24 ,  H03H3/007 ,  B81B3/00 ,  B81C1/00

CPC classification number: B81C1/00142 ,  B81B2201/0271 ,  B81C2201/019 ,  B81C2203/036 ,  B81C2203/051 ,  H03H3/0072 ,  H03H9/2447 ,  H03H9/462 ,  Y10T29/49005 ,  Y10T29/49128 ,  Y10T29/49155 ,  Y10T29/49156 ,  Y10T29/49826 ,  Y10T29/49861

Abstract: A method for fabrication of single crystal silicon micromechanical resonators using a two-wafer process, including either a Silicon-on-insulator (SOI) (104) or insulating base and resonator wafers (108) , wherein resonator anchors (122, 124) , a capacitive air gap (116) , isolation trenches (128, 130) , and alignment marks are micromachined in an active layer (114) of the base wafer; the active layer of the resonator wafer (124) is bonded directly to the active layer of the base wafer; the handle (144) and dielectric layers (140) of the resonator wafer are removed; viewing windows are opened in the active layer of the resonator wafer; masking the single crystal silicon semiconductor material active layer of the resonator wafer with photoresist material; a single crystal silicon resonator is machined in the active layer of the resonator wafer using silicon dry etch micromachining technology; and the photoresist material is subsequently dry stripped.

公开(公告)号：EP1569865B8

公开(公告)日：2008-06-18

申请号：EP03782134.5

申请日：2003-12-05

Applicant: X-FAB Semiconductor Foundries AG

Inventor： SCHWARZ, Uwe

IPC: B81C1/00 ,  B81C3/00 ,  B81B3/00

CPC classification number: B81C1/00246 ,  B81B2203/0127 ,  B81B2203/0315 ,  B81C2201/019 ,  B81C2203/036 ,  B81C2203/0728

Abstract: The invention relates to a method for producing a microelectromechanical system (MEMS) which comprises a sensor and CMOS technology-based electronics for processing the sensor signal, both being monolithically integrated in said system. To fulfil the pre-requisites for producing the electronic part (4) of the sensor (5) and the signal processing electronics using CMOS technology, a semiconductor wafer (2) containing a depression is bonded to a wafer with an epitaxial layer by means of said layer (3) using high-temperature fusion bonding, to form a double wafer and material is subsequently removed from one face of the double wafer. The latter is then polished until the epitaxial layer is exposed, thus creating a membrane (3a).

公开(公告)号：EP1921042A1

公开(公告)日：2008-05-14

申请号：EP06123873.9

申请日：2006-11-10

Applicant: ETA SA Manufacture Horlogère Suisse

Inventor： Marmy, Philippe ,  Helfer, Jean-Luc ,  Conus, Thierry

IPC: B81C5/00

CPC classification number: B81C99/0095 ,  B81B2201/035 ,  B81C2201/019 ,  B81C2201/056 ,  B81C2203/038 ,  B81C2203/051 ,  G04B31/004 ,  G04D3/0069 ,  Y10T29/49579

Abstract: Le procédé comporte les étapes suivantes :
a) usiner dans une première plaquette de silicium (1) un premier élément (3) ou une pluralité desdits premiers éléments (3) en maintenant lesdits éléments (3) liés par des ponts de matière (5);
b) répéter l'étape a) avec une deuxième plaquette de silicium (2) pour usiner un deuxième élément (4), de forme différente de celle du premier élément (3), ou une pluralité desdits deuxièmes éléments (4);
c) à l'aide de moyens de positionnement (6, 7), appliquer face contre face les premiers et deuxièmes éléments (3, 4) ou les premières et deuxièmes plaquettes (1, 2);
d) effectuer une oxydation de l'ensemble formé à l'étape c) et
e) séparer les pièces (10) des plaquettes (1, 2).
Pièces de micromécanique horlogère obtenue selon le procédé.

Abstract translation: 该方法包括加工元件（3），例如 多层微机械部件的孔眼宝石。 在商业硅晶片（1）中使用物理或化学元素（10），其中该部分由商业单晶或多晶硅制成。 重复加工步骤以加工另一个元件（4），例如 固体宝石，与另一个商业硅晶片（2）。 元件或晶片通过使用孔（6）和槽而面对面地施加以形成组件。 允许组件经历氧化，并且该部件与晶片分离。

公开(公告)号：EP1902780A2

公开(公告)日：2008-03-26

申请号：EP08000283.5

申请日：2003-02-25

Applicant: Hitachi Chemical Co., Ltd.

Inventor： The designation of the inventor has not yet been filed

IPC: B01J19/00 ,  B01L3/00

CPC classification number: B01L3/502707 ,  B01J19/0093 ,  B01J2219/00783 ,  B01J2219/00788 ,  B01J2219/00822 ,  B01J2219/00833 ,  B01J2219/0086 ,  B01J2219/00869 ,  B01L2200/12 ,  B01L2300/0816 ,  B01L2300/0838 ,  B01L2300/0874 ,  B01L2300/0887 ,  B01L2400/0481 ,  B01L2400/0655 ,  B81B2201/051 ,  B81C1/00119 ,  B81C2201/019 ,  B81C2203/032 ,  Y10T156/10

Abstract: A support unit for a microfluidic system includes a first support; a first adhesive layer provided on a surface of the first support; and a hollow filament laid on a surface of the first adhesive layer to have an arbitrary shape and functioning as a flow channel layer of the microfluidic system.

Abstract translation: 用于微流体系统的支撑单元包括第一支撑件; 设置在所述第一支撑体的表面上的第一粘合剂层; 以及放置在第一粘合剂层的表面上以具有任意形状并用作微流体系统的流动通道层的中空细丝。 在第一支撑件上不设置用于容纳中空细丝的凹槽。

公开(公告)号：EP1894234A2

公开(公告)日：2008-03-05

申请号：EP06721019.5

申请日：2006-02-24

Applicant: Silicon Genesis Corporation

Inventor： HENLEY, Francois, J. ,  KIRK, Harry, Robert ,  SULLIVAN, James, Andrew

IPC: H01L21/46 ,  H01L21/30 ,  H01L21/00

CPC classification number: H01L21/2007 ,  B81C1/00357 ,  B81C2201/019 ,  H01L21/6835 ,  H01L21/76254 ,  H01L2221/68359

Abstract: A multilayered substrate structure comprising one or more devices, e.g., optoelectronic, integrated circuit. The structure has a handle substrate, which is characterized by a predetermined thickness and a Young's modulus ranging from about 1 Mega Pascal to about 130 Giga Pascal. The structure also has a thickness of substantially crystalline material coupled to the handle substrate. Preferably, the thickness of substantially crystalline material ranges from about 100 microns to about 5 millimeters. The structure has a cleaved surface on the thickness of substantially crystalline material and a surface roughness characterizing the cleaved film of less than 200 Angstroms. At least one or more optoelectronic devices is provided on the thickness of material.

公开(公告)号：EP1891479A1

公开(公告)日：2008-02-27

申请号：EP06759191.7

申请日：2006-05-05

Applicant: Dow Corning Corporation

Inventor： HEEJOON, Ahn ,  NUZZO, Ralph ,  SHIM, Anne

IPC: G03F7/00 ,  B41M3/00 ,  B41M1/34

CPC classification number: G03F7/0002 ,  B41M1/34 ,  B41M3/003 ,  B81C1/0038 ,  B81C2201/019 ,  B81C2201/0191 ,  B82Y10/00 ,  B82Y40/00

Abstract: The present invention provides a method of sub-micron decal transfer lithography. The method includes forming a first pattern in a surface of a first silicon-containing elastomer (200), bonding at least a portion of the first pattern to a substrate (210), and etching (220) a portion of at least one of the first silicon-containing elastomer and the substrate.