公开(公告)号：EP3255635A1

公开(公告)日：2017-12-13

申请号：EP17169670.1

申请日：2017-05-05

申请人： Altera Corporation

发明人： Chu, Pohrong Rita

IPC分类号： G11C7/10 ,  G11C8/16

CPC分类号： G11C8/12 ,  G06F5/00 ,  G06F9/30141 ,  G11C7/1075 ,  G11C8/00 ,  G11C8/16

摘要： Integrated circuits may include memory element circuitry. The memory element circuitry may include multiple dual-port memory elements that are controlled to effectively form a multi-port memory element having multiple read and write ports. A respective bank of dual-port memory elements may be coupled to each write port. Write data may be received concurrently over one or more of the write ports and stored on the banks. Switching circuitry may be coupled between the banks and the read ports of the memory element circuitry. The switching circuitry may be controlled using read control signals generated by logic XOR-based control circuitry. The control circuitry may include dual-port memory elements that store addressing signals associated with the write data. The read control signals may control the switching circuitry to selectively route the most-recently written data to corresponding read ports during a data read operation.

摘要翻译： 集成电路可以包括存储器元件电路。 存储器元件电路可以包括多个双端口存储器元件，其被控制以有效地形成具有多个读取和写入端口的多端口存储器元件。 相应的双端口存储器元件组可以耦合到每个写入端口。 写入数据可以同时通过一个或多个写入端口接收并存储在存储体上。 开关电路可以耦合在存储体元件电路的读取端口和存储体之间。 可以使用由基于逻辑XOR的控制电路生成的读取控制信号来控制开关电路。 控制电路可以包括存储与写入数据相关联的寻址信号的双端口存储器元件。 读取控制信号可以控制开关电路在数据读取操作期间选择性地将最近写入的数据路由到对应的读取端口。

公开(公告)号：EP3022738B1

公开(公告)日：2017-02-01

申请号：EP14776976.4

申请日：2014-09-18

申请人： Qualcomm Incorporated

发明人： DONG, Xiangyu

IPC分类号： G11C11/00 ,  G11C11/16 ,  G11C11/56 ,  G11C13/00 ,  G11C17/02 ,  G11C17/14 ,  G11C7/10 ,  G11C8/16

CPC分类号： G11C11/1673 ,  G11C7/1075 ,  G11C8/16 ,  G11C11/005 ,  G11C11/16 ,  G11C11/1659 ,  G11C11/56 ,  G11C11/5671 ,  G11C13/0002 ,  G11C17/02 ,  G11C17/14 ,  G11C2213/74 ,  G11C2213/79

公开(公告)号：EP3080812A1

公开(公告)日：2016-10-19

申请号：EP14812468.8

申请日：2014-12-12

申请人： Commissariat à l'Energie Atomique et aux Energies Alternatives

发明人： HARRAND, Michel

IPC分类号： G11C7/10 ,  G06F11/10 ,  G11C8/16 ,  G11C13/00

CPC分类号： G11C13/0069 ,  G06F11/1048 ,  G06F11/1068 ,  G11C7/1021 ,  G11C7/1075 ,  G11C8/10 ,  G11C8/12 ,  G11C8/16 ,  G11C11/418 ,  G11C11/419 ,  G11C13/0023 ,  G11C13/004 ,  G11C13/0064 ,  G11C14/009 ,  G11C16/10 ,  G11C29/52 ,  G11C2013/0076 ,  G11C2013/0085

摘要： The invention relates to a system (100) comprising: a first memory (101) comprising several portions (Si) of one or more pages (Pi,j) each, said memory (101) comprising first (PTR) and second (PTW) ports that can simultaneously access, for reading and writing respectively, two distinct pages (Pi,j) of portions (Si) of the memory (101); and a control circuit (103) capable of performing write operations to the pages (Pi,j) of the memory (101), each write operation to a page (Pi,j) of the memory (101) requiring a reading step of a former datum on said page (Pi,j) via the first port (PTR), and comprising a writing step of a new datum to the page (Pi,j) via the second port (PTW), taking account of the former datum.

公开(公告)号：EP2976770B1

公开(公告)日：2016-10-19

申请号：EP14727682.8

申请日：2014-05-02

申请人： Qualcomm Incorporated

发明人： CHAI, Chiaming ,  GE, Shaoping ,  LILES, Stephen, Edward ,  GARG, Kunal

IPC分类号： G11C11/412 ,  G11C7/12 ,  G11C7/10 ,  G11C11/419

CPC分类号： G11C11/413 ,  G11C7/1042 ,  G11C7/1075 ,  G11C7/12 ,  G11C11/412 ,  G11C11/419

公开(公告)号：EP2913759A4

公开(公告)日：2015-11-25

申请号：EP13869490

申请日：2013-09-26

申请人： HUAWEI TECH CO LTD

发明人： HUANG YONGBING ,  CHEN MINGYU ,  RUAN YUAN ,  CHEN LICHENG

IPC分类号： G06F13/16 ,  G11C7/10

CPC分类号： G06F12/1458 ,  G06F3/0622 ,  G06F3/0635 ,  G06F3/0683 ,  G06F13/1642 ,  G06F2212/1016 ,  G06F2212/1052 ,  G11C7/1003 ,  G11C7/1075

摘要： Embodiments of the present invention disclose a memory access processing method based on memory chip interconnection, a memory chip, and a system, which relate to the field of electronic devices, and can shorten a time delay in processing a memory access request and improve a utilization rate of system bandwidth. The method of the present invention includes: receiving, by a first memory chip, a memory access request; and if the first memory chip is not a target memory chip corresponding to the memory access request, sending, according to a preconfigured routing rule through a chip interconnect interface, the memory access request to the target memory chip corresponding to the memory access request. Embodiments of the present invention are mainly used in a process of processing a memory access request.

摘要翻译： 本发明的实施例公开了一种基于存储器芯片互连的存储器访问处理方法，存储器芯片和与电子设备领域相关的系统，并且可以缩短处理存储器访问请求的时间延迟并提高利用率 系统带宽率。 本发明的方法包括：由第一存储器芯片接收存储器访问请求; 并且如果第一存储器芯片不是与存储器访问请求相对应的目标存储器芯片，则根据通过芯片互连接口的预先配置的路由规则，将存储器访问请求发送到对应于存储器访问请求的目标存储器芯片。 本发明的实施例主要用于处理存储器访问请求的过程。

公开(公告)号：EP2368194A4

公开(公告)日：2015-01-28

申请号：EP09837847

申请日：2009-12-11

申请人： INTEL CORP

发明人： DAMA JONATHAN ,  LINES ANDREW

IPC分类号： G06F15/167 ,  G06F12/06 ,  G06F13/00

CPC分类号： G11C8/16 ,  G11C7/1075 ,  G11C8/18

摘要： A memory is described which includes a main memory array made up of multiple single-ported memory banks connected by parallel read and write buses, and a sideband memory equivalent to a single dual-ported memory bank. Control logic and tags state facilitates a pattern of access to the main memory and the sideband memory such that the memory performs like a fully provisioned dual-ported memory capable of reading and writing any two arbitrary addresses on the same cycle.

摘要翻译： 描述了一种存储器，其包括由并行读写总线连接的多个单端口存储器组成的主存储器阵列，以及等同于单个双端口存储器组的边带存储器。 控制逻辑和标签状态有助于访问主存储器和边带存储器的模式，使得存储器像完全配置的双端口存储器一样，能够在同一周期读取和写入任意两个任意地址。

公开(公告)号：EP2757483A1

公开(公告)日：2014-07-23

申请号：EP14151614.6

申请日：2014-01-17

申请人： Samsung Electronics Co., Ltd

发明人： Yun, Sung-Hwan ,  Kim, Sei-Jin

IPC分类号： G06F13/38

CPC分类号： G11C7/1075 ,  G06F12/0246 ,  G06F13/382 ,  G06F13/385

摘要： An apparatus and a method capable of selectively extending a memory in a terminal are provided. The apparatus includes a socket unit into which an external memory having a built-in Random Access Memory (RAM) is inserted, and a controller that performs a control operation for moving data stored in a RAM of the terminal to the RAM of the external memory and for securing available space of the RAM of the terminal, when the external memory having the built-in RAM is inserted into the socket unit.

摘要翻译： 提供一种能够选择性地扩展终端中的存储器的装置和方法。 该装置包括插座单元，其中插入有内置随机存取存储器（RAM）的外部存储器，以及控制器，其执行用于将存储在终端的RAM中的数据移动到外部存储器的RAM的控制操作 并且当具有内置RAM的外部存储器插入到插座单元中时，用于确保终端的RAM的可用空间。

公开(公告)号：EP2425346A4

公开(公告)日：2014-05-07

申请号：EP10770092

申请日：2010-03-18

申请人： MICRON TECHNOLOGY INC

发明人： WALKER ROBERT ,  SKINNER DAN

IPC分类号： G06F12/02 ,  G06F12/06 ,  G06F12/08 ,  G06F13/16 ,  G06F13/40 ,  G11C7/10

CPC分类号： G06F12/0646 ,  G06F13/1668 ,  G06F2212/1041 ,  G11C7/1075

摘要： Embodiments of a multi-port memory device may include a plurality of ports and a plurality of memory banks some of which are native to each port and some of which are non-native to each port. The memory device may include a configuration register that stores configuration data indicative of the mapping of the memory banks to the ports. In response to the configuration data, for example, a steering logic may couple each of the ports either to one or all of the native memory banks or to one or all of the non-native memory banks.

公开(公告)号：EP2629299A1

公开(公告)日：2013-08-21

申请号：EP13002575.2

申请日：2007-12-10

申请人： Mosaid Technologies Incorporated

发明人： Hong Beom, Pyeon ,  HakJune, Oh ,  Jin-Ki, Kim

IPC分类号： G11C7/10 ,  G11C11/34 ,  H03M9/00

CPC分类号： G11C7/1045 ,  G11C7/1006 ,  G11C7/1051 ,  G11C7/1075 ,  G11C7/1078 ,  G11C2207/107

摘要： Methods and systems are provided that allow the method of access to one or more memory banks to be performed using serial access, or using parallel access. In serial mode, each link operates as an independent serial link. In contrast, during parallel mode, the links operate in common as a parallel link. Where input and output controls are received independently for each link for serial mode, a single set of input and output controls is used in common by all of the links during parallel mode.

摘要翻译： 提供了允许使用串行访问或使用并行访问来执行访问一个或多个存储体的方法和系统。 在串行模式下，每个链路都作为一个独立的串行链路运行。 相反，在并行模式下，链路作为并行链路共同工作。 在为串行模式的每个链路独立接收输入和输出控制的情况下，在并行模式下，所有链路都使用一组输入和输出控制。

公开(公告)号：EP2587486A3

公开(公告)日：2013-06-12

申请号：EP12189371.3

申请日：2012-10-22

申请人： Altera Corporation

发明人： Lewis, David

IPC分类号： G11C7/10

CPC分类号： G06F1/04 ,  G06F1/12 ,  G11C7/1075

摘要： Integrated circuits having single-port memory elements may be provided. The single-port memory elements may be controlled using a control circuit to emulate multiport functionality. In one suitable embodiment, the control circuit may be an arbitration circuit configured to execute a memory request as soon as it is received by the arbitration circuit. Requests received while a current memory access is being performed may be put on hold until the current memory access has been completed. In another suitable embodiment, the control circuit may be a sequencing circuit configured to service memory access requests from a synchronous port and an asynchronous port. Memory access requests received at the synchronous port may be serviced immediately, whereas memory access requests received at the asynchronous port may be synchronized to an internal memory clock signal and may be serviced after a preceding memory access request associated with the synchronous port has been serviced.