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    KONTAKTIERUNGSVORRICHTUNG
    142.
    发明公开
    KONTAKTIERUNGSVORRICHTUNG 审中-公开

    公开(公告)号：EP3123564A1

    公开(公告)日：2017-02-01

    申请号：EP15713190.5

    申请日：2015-03-27

    Applicant: Eugen Forschner GmbH

    Inventor： BRANDT, Thomas ,  PUSKAS, Ludwig

    IPC: H01R12/58 ,  H01R12/70

    CPC classification number: H01R12/585 ,  H01R12/7088 ,  H01R13/74 ,  H05K1/0295 ,  H05K1/115 ,  H05K2201/09409 ,  H05K2201/0979 ,  H05K2201/09954 ,  H05K2201/10181 ,  H05K2201/10303 ,  H05K2201/10962

    Abstract: The invention relates to a contact-making device for producing an electrical contact between a printed circuit board (150) accommodated in an electronics box (2) and an electrical component part (160, 162, 163), wherein the printed circuit board (150) has at least one conductor track or conductor area (F1, F2, F3, F4) having at least one contact opening (152) for receiving at least one contact pin (137; 144) arranged on the electronic component part (160, 162, 163). For simplified and permanently safe contact-making, provision is made for the printed circuit board (150) to have at least one conductor area (F1, F2, F3, F4), which has a multiplicity of contact openings (152) arranged in a regular grid pattern, said contact openings being configured to receive different electrical component parts (160, 162, 163) with in each case a different number of contact pins (137; 138; 144).

    Abstract translation: 本发明涉及一种用于在容纳在电子箱（2）中的印刷电路板（150）和电气部件（160,162,163）之间产生电接触的接触制造装置，其中印刷电路板 ）具有至少一个具有至少一个接触开口（152）的导体轨道或导体区域（F1，F2，F3，F4），用于接收布置在电子部件部件（160,162）上的至少一个接触销（137; 144） ，163）。 为了简化和永久安全的接触，为印刷电路板（150）提供具有至少一个导体面积（F1，F2，F3，F4）的导体区域（F1，F2，F3，F4），其具有多个布置在 所述接触开口被配置为接收不同的电气部件（160,162,163），每种情况下都具有不同数量的接触销（137; 138; 144）。

    KONTAKTANORDNUNG FÜR EINEN MEHRLAGIGEN SCHALTUNGSTRÄGER
    145.
    发明公开
    KONTAKTANORDNUNG FÜR EINEN MEHRLAGIGEN SCHALTUNGSTRÄGER 审中-公开
    KONTAKTANORDNUNGFÜREINEN MEHRLAGIGENSCHALTUNGSTRÄGER

    公开(公告)号：EP2932803A1

    公开(公告)日：2015-10-21

    申请号：EP13782711.9

    申请日：2013-10-24

    Applicant: Robert Bosch GmbH

    Inventor： SCHAEFER, Rainer

    IPC: H05K1/02 ,  H05K3/10 ,  H05K1/11

    CPC classification number: H05K1/0265 ,  H05K1/0263 ,  H05K1/0298 ,  H05K1/115 ,  H05K3/103 ,  H05K2201/0979 ,  H05K2201/10287 ,  H05K2201/10295

    Abstract: The invention relates to a contact arrangement (30) for a multi-layer circuit board (1a), said circuit board (1a) having at least one inner wire (2) which is contacted via at least one cutout (10). According to the invention, at least two cutouts (10) are arranged on different sides of the at least one inner wire (2), the center axes (2) of the at least two cutouts (10) having a predefined distance (a
    s ) to a target center line (2.4) of the at least one inner wire (2). The at least two cutouts (10) expose the at least one inner wire (2) in at least two contact zones (2.1) for the purpose of contact, said contact zones being arranged on different sides of the wire (2).

    Abstract translation: 本发明涉及一种用于多层电路板（1a）的接触装置（30），所述电路板（1a）具有至少一个通过至少一个切口（10）接触的内部导线（2）。 根据本发明，至少两个切口（10）布置在所述至少一个内部线（2）的不同侧上，所述至少两个切口（10）的中心轴线（2）具有预定距离（as） 到所述至少一个内部线（2）的目标中心线（2.4）。 为了接触，所述至少两个切口（10）在至少两个接触区域（2.1）中暴露所述至少一个内部线材（2），所述接触区域布置在所述线材（2）的不同侧面上。

    A PCB Strip
    146.
    发明公开
    A PCB Strip 审中-公开
    Leiterplattenstreifen

    公开(公告)号：EP2887777A1

    公开(公告)日：2015-06-24

    申请号：EP14197188.7

    申请日：2014-12-10

    Applicant: Faulhaber Precistep SA

    Inventor： Monnin, Jonas ,  Moser, Yves ,  Bellamy, Justine

    IPC: H05K1/02 ,  H02K11/00 ,  H05K1/11

    CPC classification number: H05K1/0286 ,  H02K5/225 ,  H02K11/33 ,  H02K2203/03 ,  H05K1/118 ,  H05K2201/094 ,  H05K2201/0979 ,  H05K2203/0228

    Abstract: According to the present invention there is provided a PCB strip (1,118,117,119) comprising, a first connecting portion (2) which comprises electrical contacts (5a-h) which can be electrically connected to a stator and a second connecting portion (3) which can be electrically connected to a driver, to electrically connect the stator to the driver; wherein the second connecting portion (3) comprises, a plurality of discrete connecting zones (15a-d) along the length of the second connecting portion (3), each connecting zone (15a-d) comprising electrical contacts (16a-d), where the electrical contacts (16a-d) of a connecting zone (15a-d) are suitable for electrically connecting to a driver when that connecting zone (15a-d) is closest to a free end (17) of the second connecting portion (3); and wherein the second connecting portion (3) comprises a plurality of cutting zones (6a-c) at which the second connecting portion (3) can be cut to define the free end (17) of the second connecting portion (3) so as to select one of the plurality of connecting zones (15a-d) whose electrical contacts (16a-d) are to be electrically connected to a driver.

    Abstract translation: 根据本发明，提供了一种PCB条（1,118,117,119），包括：第一连接部分（2），包括可以电连接到定子的电触头（5a-h）和可连接到第二连接部分（3）的第二连接部分 电连接到驱动器，以将定子电连接到驱动器; 其中所述第二连接部分（3）包括沿着所述第二连接部分（3）的长度的多个离散连接区域（15a-d），每个连接区域（15a-d）包括电触点（16a-d） 其中当所述连接区域（15a-d）最靠近所述第二连接部分的自由端（17）时，连接区域（15a-d）的电触头（16a-d）适于电连接到驱动器 3）; 并且其中所述第二连接部分（3）包括多个切割区域（6a-c），所述切割区域可以切割所述第二连接部分（3）以限定所述第二连接部分（3）的自由端（17），以便 选择其电触点（16a-d）与驱动器电连接的多个连接区域（15a-d）中的一个。

    WIRING BOARD FOR HAVING LIGHT EMITTING ELEMENT MOUNTED THEREON
    147.
    发明公开
    WIRING BOARD FOR HAVING LIGHT EMITTING ELEMENT MOUNTED THEREON 审中-公开
    LEITERPLATTEFÜRMONTAGE EINES LICHTEMITTIERENDEN元素DARAUF

    公开(公告)号：EP2790235A1

    公开(公告)日：2014-10-15

    申请号：EP12855243.7

    申请日：2012-11-22

    Applicant: NGK Sparkplug Co., Ltd.

    Inventor： NAGAI, Makoto ,  KAWAGUCHI, Kenzo

    IPC: H01L33/62 ,  H05K3/46 ,  H05K3/00

    CPC classification number: H05K1/184 ,  H01L25/167 ,  H01L33/62 ,  H01L2224/32225 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/73265 ,  H01L2924/30107 ,  H05K1/0257 ,  H05K1/185 ,  H05K3/4602 ,  H05K2201/0979 ,  H05K2201/10106 ,  H05K2201/10174 ,  H01L2924/00014 ,  H01L2924/00

    Abstract: To provide a light emitting element mounting wiring substrate having a light emitting element mounting section on a substrate main body having a front surface and a back surface, and a confined component electrically connected to the light emitting element, such that the confine component does not obstruct the optical path of the light emitted from the light emitting element, resulting in uniform distribution of light intensity. The light emitting element mounting wiring substrate (1a) includes a substrate main body (2) which has a front surface (3) and a back surface (4) and which includes at least an insulating substrate (2a), and a plurality of element terminals (13, 14) formed on the front surface (3) of the substrate main body (2), at least one of the element terminals having a light emitting element mounting section (fa) on the top surface thereof, wherein the wiring substrate has a Zener diode (confined element) (10) embedded in the substrate main body (2), which element is electrically connected to a light emitting element (20) mounted on the mounting section (fa) and prevents application of overvoltage to the light emitting element (20).

    Abstract translation: 为了提供一种在具有前表面和背面的基板主体上具有发光元件安装部的发光元件安装布线基板以及与发光元件电连接的限制部件，使得限制部件不会阻塞 从发光元件发射的光的光路，导致光强度的均匀分布。 发光元件安装用配线基板（1a）具备：具有前表面（3）和背面（4）的至少包含绝缘基板（2a）的基板主体（2）和多个元件 形成在基板主体（2）的前表面（3）上的端子（13,14）中的至少一个元件端子在其顶表面上具有发光元件安装部分（fa），其中布线基板 具有嵌入在基板主体（2）中的齐纳二极管（限制元件）（10），该元件电连接到安装在安装部分（fa）上的发光元件（20），并且防止对光线施加过电压 发光元件（20）。

    INTERPOSER HAVING MOLDED LOW CTE DIELECTRIC
    148.
    发明公开
    INTERPOSER HAVING MOLDED LOW CTE DIELECTRIC 审中-公开
    与形状的电介质膨胀系数低ZWISCHENSTÜCK

    公开(公告)号：EP2700090A1

    公开(公告)日：2014-02-26

    申请号：EP12719539.4

    申请日：2012-04-19

    Applicant: Tessera, Inc.

    Inventor： HABA, Belgacem ,  MOHAMMED, Ilyas

    IPC: H01L21/48 ,  H01L23/498

    CPC classification number: H01L21/486 ,  H01L23/49827 ,  H01L23/49861 ,  H01L23/49894 ,  H01L2224/16225 ,  H01L2924/09701 ,  H01L2924/15311 ,  H05K3/4046 ,  H05K2201/0979 ,  H05K2201/10378 ,  H05K2201/10674

    Abstract: A method for making an interconnection component is disclosed, including forming a plurality of metal posts extending away from a reference surface. Each post is formed having a pair of opposed end surface and an edge surface extending therebetween. A dielectric layer is formed contacting the edge surfaces and filling spaces between adjacent ones of the posts. The dielectric layer has first and second opposed surfaces adjacent the first and second end surfaces. The dielectric layer has a coefficient of thermal expansion of less than 8 ppm/° C. The interconnection component is completed such that it has no interconnects between the first and second end surfaces of the posts that extend in a lateral direction. First and second pluralities of wettable contacts are adjacent the first and second opposed surfaces. The wettable contacts are usable to bond the interconnection component to a microelectronic element or a circuit panel.

    A METHOD FOR PROCESSING A THIN FILM SUBSTRATE
    150.
    发明授权
    A METHOD FOR PROCESSING A THIN FILM SUBSTRATE 有权
    方法处理的薄膜基板

    公开(公告)号：EP1621054B1

    公开(公告)日：2011-09-14

    申请号：EP04728728.9

    申请日：2004-04-21

    Applicant: JonDeTech AB

    Inventor： MARTIN, Hans Göran Evald ,  HJORT, Klas Anders ,  LINDBERG, Mikael Peter Erik

    IPC: H05K3/18

    CPC classification number: H05K3/0041 ,  G01K2211/00 ,  H01L2924/0002 ,  H05K1/115 ,  H05K3/002 ,  H05K2201/09609 ,  H05K2201/0979 ,  H05K2203/092 ,  H01L2924/00

    Abstract: The present invention comprises a processed thin film substrate (10) and a method therefore, in order to produce a flexible printed circuit card, having a plurality of microvias going or passing through the thin film substrate and electrically connected along faced-away surfaces, in order to form an electric circuit. A first a number of real nano-tracks are filled with a first material (M1), having good electric properties, for the formation of a first number of, here denominated, first vias (V10, V30, V50), that a second number of real nano-tracks are filled with a second material (M2), having good electric properties, for the formation of a second number of, here denominated, second vias (V20, V40, V60). The first material (M1) and the second material (M2) of said first and second vias (V10-V60) are chosen having mutually different thermoelectric properties. A material surface-applied to the thin film substrate, coated on both sides (10a, 10b) of the thin film substrate (10), is distributed and/or adapted in order to allow the electrical interconnection of first vias, allocated the first material (M1), with second vias, allocated the second material (M2), and that a first via (V10) included in a series connection and a last via (V60) included in the series connection are serially co-ordinated in order to form an electric thermocouple (100) or other circuit arrangement.

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