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    Write contention-free, noise-tolerant multiport bitcell
    12.
    发明公开
    Write contention-free, noise-tolerant multiport bitcell 审中-公开
    写无竞争，耐噪声的多端口位单元

    公开(公告)号：EP2648187A3

    公开(公告)日：2017-10-11

    申请号：EP13161832.4

    申请日：2013-03-29

    申请人： NXP USA, Inc.

    发明人： Ashok, Ambica ,  Ramaraju, Ravindraraj ,  Russell, Andrew C

    IPC分类号： G11C8/16 ,  G11C8/14 ,  G11C11/419 ,  G11C7/12 ,  G11C7/18

    CPC分类号： G11C8/16 ,  G11C7/12 ,  G11C7/18 ,  G11C8/14 ,  G11C11/419

    摘要： A multi-port memory cell (112) of a multi-port memory array (104) includes a first inverter (206) that is disabled by a first subset (WWL0-3) of a plurality of write word lines and a second inverter (204), cross coupled with the first inverter (206), wherein the second inverter (204) is disabled by a second subset (WWL4-7) of the plurality of write word lines. A first selection circuit has data inputs coupled to a first subset of a plurality of write bit lines, selection inputs coupled to the first subset of the plurality of write word lines, and an output coupled to the input of the second inverter (204). The second selection circuit has data inputs coupled to a second subset (WBL4-7) of the plurality of write bit lines, selection inputs coupled to the second subset of the plurality of write word lines, and an output coupled to the input of the first inverter (206).

    摘要翻译： 多端口存储器阵列（104）的多端口存储器单元（112）包括由多个写字线的第一子集（WWL0-3）禁用的第一反相器（206）和第二反相器 204），与第一反相器（206）交叉耦合，其中第二反相器（204）被多个写字线的第二子集（WWL4-7）禁止。 第一选择电路具有耦合到多个写入位线的第一子集的数据输入，耦合到多个写入字线的第一子集的选择输入以及耦合到第二反相器（204）的输入的输出。 第二选择电路具有耦合到多个写入位线的第二子集（WBL4-7）的数据输入，耦合到多个写入字线的第二子集的选择输入以及耦合到第一 逆变器（206）。

    IN-BAND BEATING REMOVAL FOR A MEMS GYROSCOPE
    13.
    发明授权
    IN-BAND BEATING REMOVAL FOR A MEMS GYROSCOPE 有权
    针对MEMS陀螺仪的带内跳动

    公开(公告)号：EP3071931B1

    公开(公告)日：2017-08-30

    申请号：EP13859593.9

    申请日：2013-11-22

    申请人： NXP USA, Inc.

    发明人： CASSAGNES, Thierry ,  BEAULATON, Hugues ,  CORNIBERT, Laurent ,  TEO, Yean Ling

    IPC分类号： G01C19/5726 ,  G06F1/08

    CPC分类号： G01C19/5726 ,  G01C19/04 ,  G06F1/08 ,  G06F1/1694 ,  H04L7/033 ,  H04L7/06

    摘要： A vibration gyroscope circuitry (VCIRC) connectable to a vibrating MEMS gyroscope (VMEMS). The circuitry comprises drive circuitry (DRIVE) arranged to drive, when the circuitry is connected, the vibration MEMS gyroscope (VMEMS) and a measurement unit (DMU) which provides a drive measurement voltage signal (DMV) forming a measure of a displacement of a mass along a drive axis. A sense circuitry (SENSE) is arranged to process a sense measurement signal of the vibration MEMS gyroscope (VMEMS) forming a measure for a displacement of the mass along a sense axis. A digital sample clock generator (SCG) is arranged to generate a sample clock signal (SCLK) from an input signal (FDxy) derivable from a drive measurement voltage signal (DMV). The sample clock generator (SCG) comprises an oscillator (HFOSC) arranged to generate a master clock (MOSC), and a counter unit (OSCCNTR) arranged to count master clock periods during one period of the input signal. The clock generator also comprises a number count monitor (NCM) arranged to determine during how many input signal periods the number count stays constant, and to compare the number of constant periods (Ncp) with a critical number of constant periods (Ncp_crit). A frequency shifter (FSH) will trigger the oscillator to shift the master clock frequency whenever the number count monitor (NCM) has determined that the number of constant periods (Ncp) exceeds the critical number of constant periods (Ncp_crit).

    摘要翻译： 振动陀螺仪电路（VCIRC）可连接到振动MEMS陀螺仪（VMEMS）。 该电路包括驱动电路（驱动器），该驱动电路被布置成当连接电路时驱动振动MEMS陀螺仪（VMEMS）和提供驱动器测量电压信号（DMV）的测量单元（DMU），该驱动器测量电压信号形成 沿驱动轴的质量。 感测电路（SENSE）被布置为处理振动MEMS陀螺仪（VMEMS）的感测测量信号，形成沿着感测轴线的质量位移的量度。 数字采样时钟发生器（SCG）被布置为从可从驱动测量电压信号（DMV）导出的输入信号（FDxy）中产生采样时钟信号（SCLK）。 采样时钟发生器（SCG）包括设置为产生主时钟（MOSC）的振荡器（HFOSC）和设置为在输入信号的一个周期期间对主时钟周期进行计数的计数器单元（OSCCNTR）。 时钟发生器还包括数量计数监视器（NCM），用于确定在多少个输入信号周期期间数量计数保持恒定，并将恒定周期数（Ncp）与临界数量的恒定周期（Ncp_crit）进行比较。 每当计数监视器（NCM）确定恒定周期数（Ncp）超过临界恒定周期数（Ncp_crit）时，移频器（FSH）将触发振荡器移动主时钟频率。

    CAN FD END-OF-FRAME DETECTOR, CAN BIT STREAM PROCESSING DEVICE, METHOD FOR DETECTING THE END OF A CAN FD FRAME, AND METHOD OF OPERATING A CAN BIT STREAM PROCESSOR
    14.
    发明授权
    CAN FD END-OF-FRAME DETECTOR, CAN BIT STREAM PROCESSING DEVICE, METHOD FOR DETECTING THE END OF A CAN FD FRAME, AND METHOD OF OPERATING A CAN BIT STREAM PROCESSOR 有权
    CAN FD帧结束检测器，CAN位流处理装置，检测CANFD帧结束的方法以及操作CAN位流处理器的方法

    公开(公告)号：EP3050261B1

    公开(公告)日：2017-06-21

    申请号：EP13831966.0

    申请日：2013-09-27

    申请人： NXP USA, Inc.

    发明人： GACH, Robert

    IPC分类号： H04L12/413 ,  B60R16/023

    CPC分类号： H04L47/10 ,  H04L12/40039 ,  H04L12/4135 ,  H04L69/22 ,  H04L2012/40215

    摘要： A CAN FD frame comprises one or more portions provided at a normal bit rate that includes an end-of-frame field consisting of a succession of at least seven recessive bits. A method for detecting the end-of-frame of a CAN FD frame in an input bit stream entails providing a recessive bit count; defining a stretched bit transmission time longer than the bit transmission time associated with the high data rate; stretching the bit transmission time of each dominant bit succeeding a recessive bit in the input bit stream to the stretched bit transmission time to generate a conditioned input bit stream; sampling the conditioned input bit stream at a bit counter rate to generate a sampled bit stream; resetting the recessive bit count in response to each dominant bit in the sampled bit stream; and incrementing the recessive bit count in response to each recessive bit in the sampled bit stream.

    摘要翻译： CAN FD帧包括以正常比特率提供的一个或多个部分，帧末端字段由连续的至少七个隐性比特组成。 一种用于检测输入比特流中的CANFD帧的帧结束的方法需要提供隐性比特计数; 定义比与所述高数据速率相关联的比特发送时间更长的扩展比特发送时间; 将位于输入比特流中的隐性比特之后的每个显性比特的比特发送时间扩展到扩展比特发送时间以生成经调节的输入比特流; 以比特计数率对经调节的输入比特流进行采样以生成采样比特流; 响应于采样位流中的每个显性位重置隐性位计数; 并且响应于采样位流中的每个隐性位来增加隐性位计数。

    Leadframes, air-cavity packages, and electronic devices with offset vent holes, and methods of their manufacture
    15.
    发明公开
    Leadframes, air-cavity packages, and electronic devices with offset vent holes, and methods of their manufacture 有权
    引线框架，气腔封装和带有偏置通气孔的电子设备及其制造方法

    公开(公告)号：EP2704192A3

    公开(公告)日：2017-06-14

    申请号：EP13179590.8

    申请日：2013-08-07

    申请人： NXP USA, Inc.

    发明人： Bowles, Philip H. ,  Hooper, Stephen R.

    IPC分类号： H01L23/495 ,  H01L23/498 ,  H01L23/10 ,  H01L23/04

    CPC分类号： H01L23/10 ,  H01L23/49548 ,  H01L23/49861 ,  H01L2924/0002 ,  H01L2924/00

    摘要： A leadframe (300, 700) (e.g., incorporated in a device package) includes a feature (310, 322, 710, 722) (e.g., a die pad or lead) with a vent hole (336, 736) formed between first and second opposed surfaces (410, 412). The cross-sectional area of the vent hole varies substantially between the surfaces (e.g., the vent hole has a constricted portion (460)). The vent hole may be formed from a first opening (420) extending from the first surface toward the second surface to a first depth (452) that is less than a thickness (450) of the leadframe feature, and a second opening (430) extending from the second surface toward the first surface to a second depth (454) that is less than the thickness of the leadframe feature, but that is large enough for the second opening to intersect the first opening. Vertical central axes (428, 429) of the openings are horizontally offset from each other, and the constricted portion of the vent hole corresponds to the intersection of the openings.

    摘要翻译： 引线框架（300,700）（例如，并入器件封装中）包括具有形成在第一和第二引线框之间的通气孔（336,736）的特征（310,322,710,722）（例如，管芯焊盘或引线） 第二相对表面（410,412）。 通气孔的横截面积在表面之间基本上变化（例如，通气孔具有收缩部分（460））。 通气孔可以由从第一表面朝向第二表面延伸到小于引线框架特征的厚度（450）的第一深度（452）的第一开口（420）和第二开口（430）形成， 从所述第二表面朝向所述第一表面延伸到小于所述引线框架特征的厚度但是足够大以使所述第二开口与所述第一开口相交的第二深度（454）。 开口的垂直中心轴线（428,429）彼此水平偏移，并且通风孔的收缩部分对应于开口的交点。

    INTEGRATED CIRCUITS AND DEVICES WITH INTERLEAVED TRANSISTOR ELEMENTS, AND METHODS OF THEIR FABRICATION
    18.
    发明公开
    INTEGRATED CIRCUITS AND DEVICES WITH INTERLEAVED TRANSISTOR ELEMENTS, AND METHODS OF THEIR FABRICATION 审中-公开
    集成电路和器件嵌套的晶体管元件和方法及其

    公开(公告)号：EP3159931A2

    公开(公告)日：2017-04-26

    申请号：EP16192359.4

    申请日：2016-10-05

    申请人： NXP USA, Inc.

    发明人： Fraser, Michael L ,  Danaher, Frank E ,  Fender, Jason R

    IPC分类号： H01L27/02 ,  H01L27/085

    CPC分类号： H01L27/085 ,  H01L21/82 ,  H01L27/0207 ,  H01L27/0211 ,  H01P1/15 ,  H03K17/6871

    摘要： A monolithic integrated circuit includes first (424) and second (420) pluralities of parallel-connected transistor elements (e.g., transistor fingers). To spread heat in the IC, the first and second pluralities of transistor elements are interleaved with each other and arranged in a first row (474). The IC also may include third (434) and fourth (430) pluralities of parallel-connected transistor elements arranged in a second row (476). The transistor elements in the first row may be series and shunt transistors of an RF switch transmit path, and the transistor elements in the second row may be series and shunt transistors of an RF switch receive path. During a transmit mode of operation, the series transistors in the transmit path and the shunt transistors in the receive path are closed. During a receive mode of operation, the shunt transistors in the transmit path and the series transistors in the receive path are closed.

    摘要翻译： 一种单片集成电路，包括并联连接的晶体管元件（例如，晶体管的手指）的第一（424）和第二（420）的多个。 在IC扩散热量，晶体管元件的第一和第二多个交错海誓山盟和在第一行（474），其布置。 因此，该IC可包括在第二排（476），其设置并联连接的晶体管元件的第三（434）和第四（430）的多个。 第一行中的晶体管元件可以是串联和RF开关发送路径的分流晶体管，并且所述第二行中的晶体管元件可以是串联和RF开关的分流晶体管接收路径。在操作期间的发射模式，该系列 在发射路径和接收路径中的并联晶体管的晶体管是关闭的。 在操作过程中的接收模式中，在发送路径中的旁路晶体管，并在接收路径中的串联晶体管是关闭的。

    INTEGRATED CIRCUIT WITH POWER SAVING FEATURE
    20.
    发明公开
    INTEGRATED CIRCUIT WITH POWER SAVING FEATURE 审中-公开
    INTEGRIERTE SCHALTUNG MIT STROMSPARFUNKTION

    公开(公告)号：EP3147944A1

    公开(公告)日：2017-03-29

    申请号：EP16189794.7

    申请日：2016-09-20

    申请人： NXP USA, Inc.

    发明人： Jarrar, Anis M ,  Tipple, David ,  Warner, Jeff

    IPC分类号： H01L27/02 ,  G06F17/50 ,  H01L23/528 ,  H01L27/092

    CPC分类号： H01L23/5228 ,  G06F17/5077 ,  G06F2217/78 ,  H01L21/823871 ,  H01L23/485 ,  H01L23/5286 ,  H01L27/0207 ,  H01L27/0629 ,  H01L27/0688 ,  H01L27/092

    摘要： An integrated circuit includes a first transistor (16) including a first current electrode, a second current electrode, and a bulk tie; a first conductive line coupled between the first current electrode and a first supply voltage (VDD); and a second conductive line coupled to the second current electrode. A resistance of the second conductive line is at least 5 percent greater than a resistance of the first conductive line. The bulk tie is coupled to a second supply voltage (VBB). The first supply voltage is different than the second supply voltage.

    摘要翻译： 一种集成电路包括：第一晶体管（16），包括第一电流电极，第二电流电极和大块接头; 耦合在第一电流电极和第一电源电压（VDD）之间的第一导线; 以及耦合到所述第二电流电极的第二导线。 第二导线的电阻比第一导线的电阻大至少5％。 大块连接件耦合到第二电源电压（VBB）。 第一电源电压不同于第二电源电压。