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    HIGH FREQUENCY SIGNAL AMPLIFYING CIRCUITRY
    11.
    发明公开
    HIGH FREQUENCY SIGNAL AMPLIFYING CIRCUITRY 审中-公开
    HOCHFREQUENZSIGNALVERSTÄRKUNGSSCHALTUNG

    公开(公告)号：EP3043470A1

    公开(公告)日：2016-07-13

    申请号：EP16150170.5

    申请日：2016-01-05

    Applicant: Kabushiki Kaisha Toshiba

    Inventor： Takagi, Kazutaka ,  Tomita, Naotaka

    IPC: H03F1/02 ,  H03F3/60 ,  H03F1/08 ,  H03F3/195

    CPC classification number: H03F1/0288 ,  H03F1/086 ,  H03F3/195 ,  H03F3/604 ,  H03F2200/153 ,  H03F2200/451 ,  H03F2203/45528

    Abstract: A high frequency signal amplifying circuitry of an embodiment includes a first splitter (102), a first amplifier (1A), a second amplifier (1B), a loop oscillation suppressor (Rc-1), and a combiner (104). The first amplifier (1A) includes a second splitter (14A), a first carrier amplifier (20A), a first peak amplifier (18A), and a first combiner (24A). The second amplifier (1B) includes a third splitter (14B), a second carrier amplifier (20B), a second peak amplifier (18B), and a second combiner (24B). The second carrier amplifier (20B) being adjacent to an associated the first carrier amplifier (20A). The loop oscillation suppressor (Rc-1) located between the second carrier amplifier (20B) and the associated first carrier amplifier (20A).

    Abstract translation: 实施例的高频信号放大电路包括第一分路器（102），第一放大器（1A），第二放大器（1B），环路振荡抑制器（Rc-1）和组合器（104）。 第一放大器（1A）包括第二分路器（14A），第一载波放大器（20A），第一峰值放大器（18A）和第一组合器（24A）。 第二放大器（1B）包括第三分离器（14B），第二载波放大器（20B），第二峰值放大器（18B）和第二组合器（24B）。 第二载波放大器（20B）与相关联的第一载波放大器（20A）相邻。 位于第二载波放大器（20B）和相关联的第一载波放大器（20A）之间的环路振荡抑制器（Rc-1）。

    DOHERTY AMPLIFIER
    12.
    发明公开
    DOHERTY AMPLIFIER 审中-公开
    多尔蒂VERSTÄRKER

    公开(公告)号：EP3043469A1

    公开(公告)日：2016-07-13

    申请号：EP15201129.2

    申请日：2015-12-18

    Applicant: Kabushiki Kaisha Toshiba

    Inventor： Takagi, Kazutaka ,  Tomita, Naotaka

    IPC: H03F1/02 ,  H03F1/56 ,  H03F3/60 ,  H03F1/42 ,  H03F3/24

    CPC classification number: H03F1/0288 ,  H03F1/42 ,  H03F1/565 ,  H03F3/211 ,  H03F3/245 ,  H03F3/604 ,  H03F2200/09 ,  H03F2200/111 ,  H03F2200/391 ,  H03F2200/451 ,  H03F2200/543 ,  H03F2200/75 ,  H03F2203/21106

    Abstract: A Doherty amplifier (1) of an embodiment includes an input terminal (10), an output terminal (20), a splitter (12), a combiner, a carrier amplifier (14), a peak amplifier (16). The carrier amplifier includes a first input-side two-port network (C1) connected to a first output of the splitter, a first amplifier (C2) connected to an output of the first input-side two-port network, and a first output-side two-port network (C3) connected between an output of the first amplifier and a first input of the combiner. The peak amplifier includes a second input-side two-port network (P1) connected to the second output of the splitter, a second amplifier (P2) connected to an output of the second input-side two-port network, and a second output-side two-port network (P3) connected between an output of the second amplifier and a second input of the combiner. The combiner is a parallel-connected load type having a parallel connection of the output-side two-port network of the carrier amplifier and the output-side two-port network of the peak amplifier for the output terminal at a combining point (18). The load admittance at the combining point is expressed using a complex number.

    Abstract translation: 一个实施例的Doherty放大器（1）包括输入端（10），输出端（20），分路器（12），组合器，载波放大器（14），峰值放大器（16）。 载波放大器包括连接到分路器的第一输出的第一输入端双端口网络（C1），连接到第一输入侧双端口网络的输出的第一放大器（C2）和第一输出端 （C3）连接在第一放大器的输出端和组合器的第一输入端之间。 峰值放大器包括连接到分路器的第二输出的第二输入端双端口网络（P1），连接到第二输入侧双端口网络的输出的第二放大器（P2）和第二输出端 （P3）连接在第二放大器的输出端和组合器的第二输入端之间。 组合器是并联连接的负载类型，其在载波放大器的输出侧双端口网络和用于输出端子的组合点（18）处的峰值放大器的输出侧双端口网络并联， 。 组合点的负载导纳用复数表示。

    Semiconductor device
    16.
    发明公开
    Semiconductor device 有权
    HALBLEITERVORRICHTUNG MIT MEHREREN AKTIVEN REGIONEN UND INEINANDERGREIFENDEN SOURCE- DRAIN UND GATEELEKTRODEN

    公开(公告)号：EP2053660A1

    公开(公告)日：2009-04-29

    申请号：EP08253478.5

    申请日：2008-10-24

    Applicant: Kabushiki Kaisha Toshiba

    Inventor： Takagi, Kazutaka

    IPC: H01L29/06 ,  H01L29/417 ,  H01L29/423 ,  H01L29/20 ,  H01L29/24 ,  H01L29/772

    CPC classification number: H01L29/41758 ,  H01L21/8213 ,  H01L21/8252 ,  H01L21/84 ,  H01L27/0605 ,  H01L29/0696 ,  H01L29/1608 ,  H01L29/2003 ,  H01L29/4238 ,  H01L29/772

    Abstract: Electrode placement which applies easy heat dispersion of a semiconductor device with high power density and high exothermic density is provided for the semiconductor device including: a gate electrode, a source electrode, and a drain electrode which are placed on a first surface of a substrate 10, and have a plurality of fingers, respectively; gate terminal electrodes G1, G2, ..., G4, source terminal electrodes S1, S2, ..., S5, and a drain terminal electrode D which are placed on the first surface, and governs a plurality of fingers, respectively every the gate electrode, the source electrode, and the drain electrode; active areas AA1, AA2, ..., AA5 placed on the substrate of the lower part of the gate electrode, the source electrode, and the drain electrode; a non-active area (BA) adjoining the active areas and placed on the substrate; and VIA holes SC1, SC2, ..., SC5 connected to the source terminal electrodes, wherein the active areas are divided into a plurality of stripe shapes, and the fishbone placement of the gate electrode is performed.

    Abstract translation: 为半导体器件提供了具有高功率密度和高放热密度的半导体器件的易于热分散的电极放置，包括：栅电极，源电极和漏电极，其被放置在衬底10的第一表面上 并分别具有多个手指; 栅极端子电极G1，G2，...，G4，源极端子电极S1，S2，...，S5和漏极端子电极D，分别设置在第一表面上，并且分别控制多个指状物 栅电极，源电极和漏电极; 有源区域AA1，AA2，...，AA5放置在栅电极的下部的基板上，源电极和漏电极; 邻接有源区并放置在衬底上的非有源区（BA）; 以及连接到源极端子的VIA孔SC1，SC2，...，SC5，其中有源区被分成多个条形，并且进行栅电极的鱼骨放置。

    Semiconductor package and semiconductor module
    17.
    发明授权
    Semiconductor package and semiconductor module 有权

    公开(公告)号：EP2889952B1

    公开(公告)日：2018-10-03

    申请号：EP14181195.0

    申请日：2014-08-15

    Applicant: Kabushiki Kaisha Toshiba

    Inventor： Takagi, Kazutaka

    IPC: H01P5/107 ,  H01L23/66

    CPC classification number: H01L23/66 ,  H01L2224/48091 ,  H01L2924/0002 ,  H01L2924/16153 ,  H01P5/107 ,  H01L2924/00 ,  H01L2924/00014

    Abstract: According to one embodiment, a semiconductor package includes: a first metal body on which a part of a waveguide structure is formed; a second metal body including a mounting area for a semiconductor device and disposed on the first metal body; a line substrate on which a signal transmission line configured to communicate a waveguide with the semiconductor device mounted on the mounting area is formed; and a lid body disposed at a position facing the first metal body, interposing the second metal body and the line substrate. The lid body is made of resin, on which a structure corresponding to another waveguide structure on an extension of the waveguide structure in the first metal body is formed. The structure includes a metal-coated inner wall surface.

    HIGH FREQUENCY SEMICONDUCTOR DEVICE
    18.
    发明公开
    HIGH FREQUENCY SEMICONDUCTOR DEVICE 审中-公开
    HOCHFREQUENZ-HALBLEITERBAUELEMENT

    公开(公告)号：EP3136442A1

    公开(公告)日：2017-03-01

    申请号：EP16185107.6

    申请日：2016-08-22

    Applicant: Kabushiki Kaisha Toshiba

    Inventor： Takagi, Kazutaka

    IPC: H01L29/417 ,  H01L29/423 ,  H01L29/778 ,  H01L29/812 ,  H01L29/20

    CPC classification number: H01L29/41758 ,  H01L29/2003 ,  H01L29/201 ,  H01L29/42316 ,  H01L29/7786 ,  H01L29/812

    Abstract: A high frequency semiconductor device (10) includes a stacked body (60), a gate electrode (20), a source electrode (40) and a drain electrode (30). The gate electrode (20) includes a bending gate part (21) and a straight gate part (22). The bending gate part (21) is extended in a zigzag shape and has first and second outer edges. The source electrode (40) includes a bending source part (41) and a straight source part (42). The bending source part (41) has an outer edge spaced by a first distance from the first outer edge of the bending gate part (21) along a normal direction (17). The drain electrode (30) includes a bending drain part (31) and a straight drain part (32). The bending drain part (31) has an outer edge spaced by a second distance from the second outer edge of the bending gate part (21) along the normal direction (17).

    Abstract translation: 高频半导体器件（10）包括层叠体（60），栅电极（20），源电极（40）和漏电极（30）。 栅电极（20）包括弯曲浇口部（21）和直浇口部（22）。 弯曲门部分（21）以锯齿形延伸并具有第一和第二外边缘。 源电极（40）包括弯曲源部（41）和直线源部（42）。 弯曲源部（41）具有沿着法线方向（17）与弯曲浇口部（21）的第一外缘隔开第一距离的外缘。 漏极（30）包括弯曲排水部（31）和直线排出部（32）。 弯曲排水部分31具有沿着法线方向（17）与弯曲浇口部分（21）的第二外边缘间隔开第二距离的外边缘。

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