公开(公告)号：EP2915190A4

公开(公告)日：2016-09-14

申请号：EP13850327

申请日：2013-10-23

Applicant: RAYTHEON CO

Inventor： GOOCH ROLAND ,  DIEP BUU ,  KOCIAN THOMAS ALLAN ,  BLACK STEPHEN H ,  KENNEDY ADAM M

IPC: H01L23/48 ,  H01L21/56 ,  H01L23/544

CPC classification number: B81B7/0041 ,  B81B7/007 ,  B81C1/00269 ,  B81C2203/019 ,  H01L23/053 ,  H01L24/27 ,  H01L24/29 ,  H01L24/83 ,  H01L2224/27444 ,  H01L2224/27462 ,  H01L2224/27464 ,  H01L2224/29011 ,  H01L2224/291 ,  H01L2224/83001 ,  H01L2224/83007 ,  H01L2224/83139 ,  H01L2224/8314 ,  H01L2224/83141 ,  H01L2224/83192 ,  H01L2924/1461 ,  H01L2924/163 ,  H01L2924/00014 ,  H01L2924/014

Abstract: A method of forming a wafer level packaged circuit device includes forming a device wafer, the device wafer including a first group of one or more material layers left remaining in a first region of a substrate of the device wafer; and forming a cap wafer configured to be attached to the device wafer, the cap wafer including a second group of one or more material layers left remaining in a second region of a substrate of the cap wafer; wherein a combined thickness of the first and second groups of one or more material layers defines an integrated bond gap control structure upon bonding of the device wafer and the cap wafer.

Abstract translation: 形成晶片级封装电路器件的方法包括形成器件晶片，器件晶片包括留在器件晶片的衬底的第一区域中的第一组一个或多个材料层; 以及形成被配置为附接到所述器件晶片的盖晶片，所述盖晶片包括留在所述盖晶片的衬底的第二区域中的第二组一个或多个材料层; 其中一个或多个材料层的第一组和第二组的组合厚度在结合所述器件晶片和所述盖晶片时限定了整合的键合间隙控制结构。

公开(公告)号：EP2677538A4

公开(公告)日：2016-02-17

申请号：EP11858569

申请日：2011-03-16

Applicant: OMRON TATEISI ELECTRONICS CO

Inventor： OKUNO TOSHIAKI ,  INOUE KATSUYUKI ,  FUJIWARA TAKESHI ,  SEKI TOMONORI

IPC: H01L23/02

CPC classification number: H01L21/78 ,  B81C1/00269 ,  B81C1/00873 ,  B81C2203/019 ,  H01L21/50 ,  H01L23/10 ,  H01L24/03 ,  H01L24/05 ,  H01L24/27 ,  H01L24/29 ,  H01L24/32 ,  H01L24/83 ,  H01L24/94 ,  H01L2224/0345 ,  H01L2224/03462 ,  H01L2224/04026 ,  H01L2224/05551 ,  H01L2224/05552 ,  H01L2224/05554 ,  H01L2224/05555 ,  H01L2224/05557 ,  H01L2224/2745 ,  H01L2224/27462 ,  H01L2224/29005 ,  H01L2224/29007 ,  H01L2224/29011 ,  H01L2224/29012 ,  H01L2224/29013 ,  H01L2224/29014 ,  H01L2224/29082 ,  H01L2224/29083 ,  H01L2224/29099 ,  H01L2224/2919 ,  H01L2224/3201 ,  H01L2224/32225 ,  H01L2224/83101 ,  H01L2224/83801 ,  H01L2224/8385 ,  H01L2224/94 ,  H01L2924/0002 ,  H01L2924/1461 ,  H01L2924/163 ,  H01L2924/351 ,  H01L2924/3512 ,  H01L2924/00 ,  H01L2924/00012 ,  H01L2224/83 ,  H01L2224/27 ,  H01L2224/03 ,  H01L2924/00014

Abstract: A wafer level package (20A) according to the present invention is provided with a base wafer (22) having a plurality of semiconductor chips (1) mounted or formed on its surface and a cover wafer (23) opposite the base wafer (22). The base wafer (22) and the cover wafer (23) are joined so as to sandwich therebetween a frame-shaped seal frame (4) which seals the periphery of each semiconductor chip. A gap (24) is formed between respective seal frames (4) of mutually adjoining semiconductor chips (1). In the gap (24) between the respective seal frames (4) of the mutually adjoining semiconductor chips (1), a partial connect part (26) is provided, which mutually and partially connects both seal frames (4). Hereby, the occurrence of a crack in a seal frame can be avoided when dicing, while providing a wafer level package, a chip size package device and a method of manufacturing a wafer level package, which can suppress the occurrence of peel-off from a wafer even when a high-temperature process is applied after a wet process or after liquid cleaning.

Abstract translation: 一种晶片级封装（20A）雅丁到，本发明是设置有具有半导体芯片有多个（1）安装或形成在其表面与基底晶片相对的晶片盖（23）上的基体晶片（22）（22） ， 基底晶片（22）和所述盖晶片（23）以夹着框状密封框架（4），其密封每个半导体芯片的周边之间接合，从而在那里。 的间隙（24）是相互邻接的半导体芯片（1）所形成respectivement密封帧（4）之间。 在相互邻接的半导体芯片（1）的密封respectivement帧（4）之间的间隙（24），部分连接部分（26）被提供，其相互并部分地连接两个密封帧（4）。 由此，在密封框架的裂纹的发生，可避免当切割，同时提供了晶片级封装，芯片尺寸封装器件及其制造晶片级封装，其可以从一个抑制剥离的发生的方法 晶片甚至当高温工艺的湿式处理之后或清洗液体之后施用。

公开(公告)号：EP2755401A4

公开(公告)日：2015-04-08

申请号：EP12829997

申请日：2012-08-29

Applicant: OMRON TATEISI ELECTRONICS CO

Inventor： KURATANI NAOTO

IPC: H04R1/04 ,  B81B7/00 ,  H01L23/00 ,  H01L23/04 ,  H01L23/552 ,  H01L25/00 ,  H04R1/02 ,  H04R1/06 ,  H04R19/00 ,  H04R19/04 ,  H05K9/00

CPC classification number: B81B7/0064 ,  B81B2201/0257 ,  H01L23/04 ,  H01L23/552 ,  H01L24/13 ,  H01L24/16 ,  H01L24/32 ,  H01L24/48 ,  H01L24/49 ,  H01L24/73 ,  H01L2224/13144 ,  H01L2224/16225 ,  H01L2224/16227 ,  H01L2224/32225 ,  H01L2224/48091 ,  H01L2224/48137 ,  H01L2224/48227 ,  H01L2224/49175 ,  H01L2224/73204 ,  H01L2224/73265 ,  H01L2924/00014 ,  H01L2924/12041 ,  H01L2924/14 ,  H01L2924/1433 ,  H01L2924/1461 ,  H01L2924/15153 ,  H01L2924/15192 ,  H01L2924/16151 ,  H01L2924/163 ,  H01L2924/3011 ,  H01L2924/3025 ,  H04R1/04 ,  H04R1/086 ,  H04R19/005 ,  H04R19/04 ,  H01L2924/00 ,  H01L2924/00012 ,  H01L2224/45099 ,  H01L2224/45015 ,  H01L2924/207

Abstract: A package is formed by vertically stacking a cover (44) and a substrate (45). A microphone chip (42) is mounted at the top surface of a concave portion (46) provided to the cover (44), and a circuit element (43) is mounted on the upper surface of the substrate (45). The microphone chip (42) is connected to a pad (48) on the lower surface of the cover by a bonding wire (50). The circuit element (43) is connected to a pad on the upper surface of the substrate by a bonding wire. A cover-side joining portion (49) in conduction with the pad (48) on the lower surface of the cover, and a substrate-side joining portion (69) in conduction with the pad on the upper surface of the substrate, are joined by a conductive material (86). A conductive layer (55) for electromagnetic shielding is embedded inside the cover (44) near the bonding pad (48) and the cover-side joining portion (49).

公开(公告)号：EP2616859A1

公开(公告)日：2013-07-24

申请号：EP11781861.7

申请日：2011-09-05

Applicant: FCI

Inventor： DROESBEKE, Gert

IPC: G02B6/42 ,  H01L23/10

CPC classification number: G02B6/262 ,  G02B6/4214 ,  G02B6/4239 ,  H01L23/10 ,  H01L2924/0002 ,  H01L2924/163 ,  Y10T156/10 ,  H01L2924/00

Abstract: An optical coupling device comprises: a Z-reference part co-operating with a Z-reference of a first optical device, to define the location of a first optical interface of the coupling device along a direction (Z), fixation parts (17, 19), extending at different heights along this direction, adapted to be glued to the first optical device.

公开(公告)号：EP2463906A3

公开(公告)日：2013-03-06

申请号：EP11170565.3

申请日：2011-06-20

Applicant: Kabushiki Kaisha Toshiba

Inventor： Takagi, Kazutaka

IPC: H01L23/66 ,  H01L23/047 ,  H01L23/49 ,  H01L23/64

CPC classification number: H01L23/047 ,  H01L23/10 ,  H01L23/642 ,  H01L23/66 ,  H01L24/48 ,  H01L24/49 ,  H01L29/2003 ,  H01L29/41758 ,  H01L29/42316 ,  H01L29/7786 ,  H01L29/812 ,  H01L2223/6611 ,  H01L2223/665 ,  H01L2223/6655 ,  H01L2223/6666 ,  H01L2223/6688 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/4911 ,  H01L2224/49111 ,  H01L2224/49175 ,  H01L2924/00014 ,  H01L2924/07802 ,  H01L2924/12032 ,  H01L2924/1305 ,  H01L2924/13051 ,  H01L2924/1306 ,  H01L2924/13062 ,  H01L2924/13063 ,  H01L2924/13064 ,  H01L2924/1461 ,  H01L2924/16195 ,  H01L2924/163 ,  H01L2924/164 ,  H01L2924/19107 ,  H01L2924/30107 ,  H01L2924/3011 ,  H01L2224/45099 ,  H01L2924/00

Abstract: According to one embodiment, provided is a semiconductor device includes: a high frequency semiconductor chip; an input matching circuit disposed at the input side of the high frequency semiconductor chip; an output matching circuit disposed at the output side of the high frequency semiconductor chip; a high frequency input terminal connected to the input matching circuit; a high frequency output terminal connected to the output matching circuit, and a smoothing capacitor terminal connected to the high frequency semiconductor chip. The high frequency semiconductor chip, the input matching circuit and the output matching circuit are housed by one package.

Abstract translation: 根据一个实施例，提供了一种半导体器件，包括：高频半导体芯片; 输入匹配电路，设置在高频半导体芯片的输入侧; 输出匹配电路，设置在高频半导体芯片的输出侧; 连接到输入匹配电路的高频输入端; 连接到输出匹配电路的高频输出端子，以及连接到高频半导体芯片的平滑电容器端子。 高频半导体芯片，输入匹配电路和输出匹配电路由一个封装容纳。

公开(公告)号：EP1906443A2

公开(公告)日：2008-04-02

申请号：EP07004143.9

申请日：2007-02-28

Applicant: MITSUBISHI ELECTRIC CORPORATION

Inventor： Taguchi, Kazunori ,  Oota, Kenji

IPC: H01L23/051 ,  H01L23/04

CPC classification number: H01L23/051 ,  H01L24/72 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01019 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01042 ,  H01L2924/01067 ,  H01L2924/01082 ,  H01L2924/163 ,  H01L2924/3025

Abstract: A pressure-contact semiconductor device (100) includes thermal buffer plates (2) and main electrode blocks (3) having flanges (4), by which semiconductor substrate (1) having a pair of electrodes is sandwiched, disposed opposed to each side thereof, wherein the semiconductor substrate (1) is sealed in a gastight space by joining the flanges (4) to insulating container (5). The semiconductor device (100) is configured such that the outermost periphery of the semiconductor substrate (1) is enclosed by hollow cylindrical insulator (9) fitted on outer peripheries of the main electrode blocks (3) in the gastight space with O-rings (8) fitted between the main electrode blocks (3) and the cylindrical insulator (9), and sealed with reaction force from the O-rings (8).

Abstract translation: 压接触式半导体装置（100）包括具有凸缘（4）的热缓冲板（2）和主电极块（3），具有一对电极的半导体衬底（1）夹在其中，并与其每一侧相对设置 其中通过将凸缘（4）连接到绝缘容器（5）而将半导体衬底（1）密封在气密空间中。 半导体器件（100）被构造成使得半导体衬底（1）的最外周由被装配在主电极块（3）的外周上的中空圆柱形绝缘体（9）封闭在气密空间中，其中O形环 8）安装在主电极块（3）和圆筒形绝缘体（9）之间，并用来自O形环（8）的反作用力密封。

公开(公告)号：EP1198164A1

公开(公告)日：2002-04-17

申请号：EP00610102.6

申请日：2000-10-11

Applicant: Telefonaktiebolaget L M Ericsson (Publ)

Inventor： Bygdö, Hakan ,  Wilson, Andreas

IPC: H05K9/00 ,  H05K3/12

CPC classification number: H05K9/0028 ,  H01L23/10 ,  H01L23/552 ,  H01L2224/16 ,  H01L2924/00014 ,  H01L2924/16152 ,  H01L2924/163 ,  H01L2924/16315 ,  H01L2924/3025 ,  H05K3/1225 ,  H05K9/0015 ,  H01L2224/0401

Abstract: The invention relates to: A method of making a gasket (1) on a PCB (Printed Circuit Board) (2) and a PCB comprising a gasket. The object of the present invention is to provide a method of making a high quality gasket that may be conveniently customized to individual needs and which is easily integrated in a normal assembly process. The problem is solved in that the gasket (1) is made by screen printing techniques. This method has the advantage of using a technique that is already commonly used in an electronics assembly environment, and which method may implement relatively complex patterns with a relatively high precision in the layout of feature dimensions and which is relatively economic in use. The invention may e.g. be used for making customized gaskets for EMI shields on a PCB.

Abstract translation: 本发明涉及一种在PCB（印刷电路板）（2）上制造衬垫（1）的方法和包括衬垫的PCB。 本发明的目的是提供一种制造高质量垫圈的方法，其可以根据个人需要方便地定制，并且易于集成在正常组装过程中。 解决的问题是垫片（1）通过丝网印刷技术制成。 该方法具有使用已经在电子装配环境中通常使用的技术的优点，并且哪种方法可以在特征尺寸的布局中实现相对较高精度的相对复杂的图案，并且在使用中是相对经济的。 本发明可以例如。 用于在PCB上制作EMI屏蔽的定制垫圈。

公开(公告)号：EP3195358A4

公开(公告)日：2018-04-25

申请号：EP14901871

申请日：2014-09-17

Applicant: INTEL CORP

Inventor： LEE KEVIN J ,  SARASWAT RUCHIR ,  ZILLMANN UWE ,  RAO VALLURI BOB ,  LUND-LARSEN TOR ,  COWLEY NICHOLAS P

IPC: H01L27/04 ,  B81B7/02 ,  H01L21/60

CPC classification number: H04R1/04 ,  B81B7/02 ,  B81B2201/0257 ,  B81B2207/096 ,  B81C1/00158 ,  B81C2201/0132 ,  B81C2203/0109 ,  H01L21/6835 ,  H01L21/6836 ,  H01L21/76898 ,  H01L23/481 ,  H01L24/13 ,  H01L24/16 ,  H01L24/27 ,  H01L24/29 ,  H01L24/32 ,  H01L24/83 ,  H01L2221/68327 ,  H01L2221/6834 ,  H01L2221/68381 ,  H01L2224/131 ,  H01L2224/16227 ,  H01L2224/27002 ,  H01L2224/27618 ,  H01L2224/27848 ,  H01L2224/29011 ,  H01L2224/2919 ,  H01L2224/3201 ,  H01L2224/32058 ,  H01L2224/32225 ,  H01L2224/32245 ,  H01L2224/73204 ,  H01L2224/83005 ,  H01L2224/83193 ,  H01L2224/83438 ,  H01L2224/8346 ,  H01L2224/83488 ,  H01L2224/8359 ,  H01L2224/83688 ,  H01L2224/83862 ,  H01L2224/92 ,  H01L2224/9222 ,  H01L2224/92225 ,  H01L2924/1461 ,  H01L2924/15311 ,  H01L2924/161 ,  H01L2924/16151 ,  H01L2924/16152 ,  H01L2924/163 ,  H01L2924/166 ,  H04R1/406 ,  H04R19/005 ,  H04R19/04 ,  H01L2924/014 ,  H01L2924/0665 ,  H01L2924/01014 ,  H01L2924/00014 ,  H01L2924/00012 ,  H01L2224/11 ,  H01L2224/27 ,  H01L2224/83 ,  H01L2224/81 ,  H01L2221/68304

Abstract: Embodiments of the present disclosure describe a die with integrated microphone device using through-silicon vias (TSVs) and associated techniques and configurations. In one embodiment, an apparatus includes an apparatus comprising a semiconductor substrate having a first side and a second side disposed opposite to the first side, an interconnect layer formed on the first side of the semiconductor substrate, a through-silicon via (TSV) formed through the semiconductor substrate and configured to route electrical signals between the first side of the semiconductor substrate and the second side of the semiconductor substrate, and a microphone device formed on the second side of the semiconductor substrate and electrically coupled with the TSV. Other embodiments may be described and/or claimed.

公开(公告)号：EP2915190B1

公开(公告)日：2018-03-07

申请号：EP13850327.1

申请日：2013-10-23

Applicant: Raytheon Company

Inventor： GOOCH, Roland ,  DIEP, Buu ,  KOCIAN, Thomas Allan ,  BLACK, Stephen H. ,  KENNEDY, Adam M.

IPC: H01L23/48 ,  H01L21/56 ,  H01L23/544

CPC classification number: B81B7/0041 ,  B81B7/007 ,  B81C1/00269 ,  B81C2203/019 ,  H01L23/053 ,  H01L24/27 ,  H01L24/29 ,  H01L24/83 ,  H01L2224/27444 ,  H01L2224/27462 ,  H01L2224/27464 ,  H01L2224/29011 ,  H01L2224/291 ,  H01L2224/83001 ,  H01L2224/83007 ,  H01L2224/83139 ,  H01L2224/8314 ,  H01L2224/83141 ,  H01L2224/83192 ,  H01L2924/1461 ,  H01L2924/163 ,  H01L2924/00014 ,  H01L2924/014

Abstract: A method of forming a wafer level packaged circuit device includes forming a device wafer, the device wafer including a first group of one or more material layers left remaining in a first region of a substrate of the device wafer; and forming a cap wafer configured to be attached to the device wafer, the cap wafer including a second group of one or more material layers left remaining in a second region of a substrate of the cap wafer; wherein a combined thickness of the first and second groups of one or more material layers defines an integrated bond gap control structure upon bonding of the device wafer and the cap wafer.

公开(公告)号：EP3195358A1

公开(公告)日：2017-07-26

申请号：EP14901871.5

申请日：2014-09-17

Applicant: Intel Corporation

Inventor： LEE, Kevin J. ,  SARASWAT, Ruchir ,  ZILLMANN, Uwe ,  RAO, Valluri Bob ,  LUND-LARSEN, Tor ,  COWLEY, Nicholas P.

IPC: H01L27/04 ,  H01L21/60 ,  B81B7/02

CPC classification number: H04R1/04 ,  B81B7/02 ,  B81B2201/0257 ,  B81B2207/096 ,  B81C1/00158 ,  B81C2201/0132 ,  B81C2203/0109 ,  H01L21/6835 ,  H01L21/6836 ,  H01L21/76898 ,  H01L23/481 ,  H01L24/13 ,  H01L24/16 ,  H01L24/27 ,  H01L24/29 ,  H01L24/32 ,  H01L24/83 ,  H01L2221/68327 ,  H01L2221/6834 ,  H01L2221/68381 ,  H01L2224/131 ,  H01L2224/16227 ,  H01L2224/27002 ,  H01L2224/27618 ,  H01L2224/27848 ,  H01L2224/29011 ,  H01L2224/2919 ,  H01L2224/3201 ,  H01L2224/32058 ,  H01L2224/32225 ,  H01L2224/32245 ,  H01L2224/73204 ,  H01L2224/83005 ,  H01L2224/83193 ,  H01L2224/83438 ,  H01L2224/8346 ,  H01L2224/83488 ,  H01L2224/8359 ,  H01L2224/83688 ,  H01L2224/83862 ,  H01L2224/92 ,  H01L2224/9222 ,  H01L2224/92225 ,  H01L2924/1461 ,  H01L2924/15311 ,  H01L2924/161 ,  H01L2924/16151 ,  H01L2924/16152 ,  H01L2924/163 ,  H01L2924/166 ,  H04R1/406 ,  H04R19/005 ,  H04R19/04 ,  H01L2924/014 ,  H01L2924/0665 ,  H01L2924/01014 ,  H01L2924/00014 ,  H01L2924/00012 ,  H01L2224/11 ,  H01L2224/27 ,  H01L2224/83 ,  H01L2224/81 ,  H01L2221/68304

Abstract: Embodiments of the present disclosure describe a die with integrated microphone device using through-silicon vias (TSVs) and associated techniques and configurations. In one embodiment, an apparatus includes an apparatus comprising a semiconductor substrate having a first side and a second side disposed opposite to the first side, an interconnect layer formed on the first side of the semiconductor substrate, a through-silicon via (TSV) formed through the semiconductor substrate and configured to route electrical signals between the first side of the semiconductor substrate and the second side of the semiconductor substrate, and a microphone device formed on the second side of the semiconductor substrate and electrically coupled with the TSV. Other embodiments may be described and/or claimed.

Abstract translation: 本公开的实施例描述了具有使用硅通孔（TSV）和相关技术和配置的集成麦克风装置的裸片。 在一个实施例中，一种设备包括装置，该装置包括具有第一侧和与第一侧相对设置的第二侧的半导体衬底，形成在半导体衬底的第一侧上的互连层，形成的硅通孔（TSV） 通过半导体衬底并且被配置为在半导体衬底的第一侧和半导体衬底的第二侧之间路由电信号，以及形成在半导体衬底的第二侧上并且与TSV电耦合的麦克风器件。 其他实施例可以被描述和/或要求保护。