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    Method for differentiating the programming and erasing voltages in non volatile memory devices and corresponding memory device manufacturing process
    11.
    发明公开
    Method for differentiating the programming and erasing voltages in non volatile memory devices and corresponding memory device manufacturing process 有权
    一种用于在其非易失性存储器及其制造方法编程的分化和擦除电压的方法

    公开(公告)号：EP1047078A1

    公开(公告)日：2000-10-25

    申请号：EP99830235.0

    申请日：1999-04-21

    申请人： STMicroelectronics S.r.l.

    发明人： Gomiero, Enrico ,  Pio, Federico ,  Zuliani, Paola

    IPC分类号： G11C16/30 ,  G11C16/12

    CPC分类号： G11C16/12 ,  G11C16/0433 ,  G11C16/30

    摘要： This invention relates to a method of adjusting the erase/program voltage in semiconductor non-volatile memories. The memories are formed of at least one matrix of memory cells having a floating gate, a control gate, and drain and source terminals, and are organized by the byte in rows (WL) and columns (BL), each byte comprising a group of cells having respective control gates connected in parallel with one another to a common control line (CG) through a selection element of the byte switch type, and each cell being connected to a respective control column (BL) through a selection element of the bit switch type. Advantageously, a double adjustment is provided for the program voltage of the memory cells, whereby the program voltage during the erasing phase can be higher in modulo than the program voltage during the writing phase.
    This is achieved by providing respective adjusters (4,5) connected between a generator (7) of a program voltage (Vpp) and the cell matrix, or alternatively forming the bit switch element (20) inside a well (13) and the byte switch element (21) directly in the substrate.

    摘要翻译： 一种非易失性存储器部分（1）包括包含如行字线（WL）和列作为位线（BL）的存储单元（2）的矩阵。 控制电路（3）包括一编程​​电压产生器（7）施加到矩阵行，第一调整器（4）调整到擦除电压的（VppE）上的电压（VST）的调整器（25）和第二（5 ）的写入电压（VppW）的。 在擦除阶段的编程电压设定为比在写作阶段更高。 因此独立claimsoft包括用于制造半导体非易失性存储器，包括形成阱内的位开关元件和在所述衬底的一个字节开关直接元件的过程。

    Array of electrically programmable non-volatile semiconductor memory cells comprising ROM memory cells
    12.
    发明公开
    Array of electrically programmable non-volatile semiconductor memory cells comprising ROM memory cells 失效
    Elektrisch programmierbare，nichtflüchtigeHalbleiterspeicherzellenmatrix mit ROM-Speicherzellen

    公开(公告)号：EP0890985A1

    公开(公告)日：1999-01-13

    申请号：EP97830342.8

    申请日：1997-07-08

    申请人： STMicroelectronics S.r.l.

    发明人： Pio, Federico

    IPC分类号： H01L21/8247 ,  H01L27/115 ,  H01L21/8246 ,  H01L27/112

    CPC分类号： H01L27/11521 ,  H01L27/112 ,  H01L27/1126 ,  H01L27/115 ,  H01L27/11524

    摘要： Array of electrically programmable non-volatile memory cells, each cell comprising a floating gate (9;90), a control gate (12;120) coupled to a row (WL) of the array, a first electrode (7,13;70;130) associated with a column (BL1-BL8) of the array and a second electrode (6;70) separated from the first electrode by a channel region underlying said floating gate, the first electrode, the second electrode and the channel region being formed in a layer of semiconductor material (5) of a first conductivity type and having a second conductivity type, comprising at least one ROM memory cell (2;200) which is identical to the electrically programmable non-volatile memory cells and is associated with a respective row and a respective column of the array, the ROM cell (2;200) comprising means for allowing or not allowing the electrical separation between said respective column and the second electrode (6';61) of the ROM cell (2;200), if the ROM cell must store a first logic state or, respectively, a second logic state.

    摘要翻译： 阵列的电可编程非易失性存储器单元，每个单元包括浮置栅极（9; 90），耦合到阵列的行（WL）的控制栅极（12; 120），第一电极（7,13; 70 ;与所述阵列的列（BL1-BL8）相关联的第二电极（6; 70）和通过所述浮置栅极下方的沟道区域与所述第一电极分离的第二电极（6; 70），所述第一电极，所述第二电极和所述沟道区域 形成在第一导电类型和具有第二导电类型的半导体材料层（5）中，包括至少一个与电可编程非易失性存储器单元相同的ROM存储单元（2; 200），并且与 所述ROM单元（2; 200）包括用于允许或不允许所述相应列和所述ROM单元（2; 200）的所述第二电极（6'; 61）之间的电分离的装置。 200），如果ROM单元必须存储第一逻辑状态， 第二个逻辑状态。

    Method of fabrication a non-volatile semiconductor memory device with shielded single polysilicon gate memory part
    13.
    发明公开
    Method of fabrication a non-volatile semiconductor memory device with shielded single polysilicon gate memory part 失效
    制造非易失性半导体存储装置的方法与屏蔽Einpolysiliziumgate存储部

    公开(公告)号：EP0889520A1

    公开(公告)日：1999-01-07

    申请号：EP97830334.5

    申请日：1997-07-03

    申请人： STMicroelectronics S.r.l.

    发明人： Bottini, Roberta ,  Dalla Libera, Giovanna ,  Vajana, Bruno ,  Pio, Federico

    IPC分类号： H01L21/8247 ,  H01L27/115

    CPC分类号： H01L27/11521 ,  H01L27/115 ,  H01L27/11558

    摘要： Process for manufacturing a semiconductor memory device comprising the formation, in a same semiconductor material chip, of at least a first memory cell (18) comprising a MOS transistor (19) with a first gate electrode (21) and a second gate electrode (23) superimposed and respectively formed by definition in a first (12) and a second layer (17) of conductive material, and of at least a second memory cell (1) shielded by a layer (32) of shielding material for preventing the information stored in the second memory cell (1) from being accessible from the outside, said second memory cell (1) comprising a MOS transistor (2) with a floating gate electrode (4) formed simultaneously with the first gate electrode (21) of the first cell (18) by definition of said first layer of conductive material (12). Said layer of shielding material (32) is formed by definition of said second layer of conductive material (17).

    摘要翻译： 处理用于制造半导体存储器件，包括形成，在相同的半导体材料芯片，至少一个第一存储单元（18）包括具有第一栅电极（21）和第二栅电极的MOS晶体管（19）（23 ）屏蔽材料用于防止存储的信息的叠加并分别在第一（12根据定义形成的）和导电材料的第二层（17），以及至少一个第二存储单元的（1由一个层（32屏蔽）） 在从外部被访问的第二存储单元（1），所述第二存储器单元（1），其包含（2）与浮置栅电极（4）与所述第一的第一栅电极（21）同时形成的MOS晶体管 细胞（18）通过所述第一导电材料（12）的层的定义。 屏蔽材料（32）的所述层是通过导电材料（17）的所述第二层的定义形成。

    A memory device with time-shifting based emulation of reference cells
    16.
    发明公开
    A memory device with time-shifting based emulation of reference cells 有权
    Speichervorrichtung mit auf Zeitverschiebung basierender参考文献

    公开(公告)号：EP1699055A1

    公开(公告)日：2006-09-06

    申请号：EP05101660.8

    申请日：2005-03-03

    申请人： STMicroelectronics S.r.l.

    发明人： Pio, Federico ,  Bolandrina, Efrem ,  Vimercati, Daniele

    IPC分类号： G11C11/56 ,  G11C16/28

    CPC分类号： G11C11/5642 ,  G11C16/32 ,  G11C2211/5634

    摘要： A memory device (100;400) is proposed. The memory device includes a plurality of memory cells (Mc), means (115-145) for comparing a set of selected memory cells with at least one reference cell (Mr 0 -Mr 2 ;Mr) having a predefined threshold voltage, the means for comparing including means (115,120) for applying a biasing voltage having a substantially monotone time pattern to the selected memory cells and to the at least one reference cell, means (130) for detecting the reaching of a comparison current by a cell current of each selected memory cell and by a reference current of each reference cell, and logic means (145) for determining a condition of each selected memory cell according to a temporal relation of the reaching of the comparison current by the corresponding cell current and by the at least one reference current, wherein the means for comparing further includes means (220;520 j ;320 o -320 2 ,322;620 j ,622 j ) for time shifting at least one of said detections according to at least one predefined interval to emulate the comparison with at least one further reference cell having a further threshold voltage.

    摘要翻译： 提出了存储器件（100; 400）。 存储器件包括多个存储器单元（Mc），用于将所选择的存储单元组与至少一个具有预定阈值电压的参考单元（Mr 0 -Mr 2; Mr）进行比较的装置（115-145） 用于比较包括用于将具有基本上单调的时间模式的偏置电压施加到所选择的存储器单元的装置（115,120）和至少一个参考单元，用于检测比较电流达到各个电池电流的装置（130） 选择的存储单元和每个参考单元的参考电流;以及逻辑单元（145），用于根据比较电流达到相应的单元电流的时间关系和至少至少 一个参考电流，其中用于比较的装置进一步包括用于根据至少一个预定间隔到emu的时间移位所述检测中的至少一个的装置（220; 520j; 320o-3202,322; 620j，622j） 迟到与具有另一阈值电压的至少一个另外的参考单元的比较。

    Semiconducting material substrate for use in integrated circuits manufacturing processes and production method thereof
    19.
    发明公开
    Semiconducting material substrate for use in integrated circuits manufacturing processes and production method thereof 审中-公开
    半导体材料的衬底用于集成电路和制造这种衬底的方法中的制造工艺使用

    公开(公告)号：EP0980098A1

    公开(公告)日：2000-02-16

    申请号：EP98830500.9

    申请日：1998-08-11

    申请人： STMicroelectronics S.r.l.

    发明人： Pio, Federico

    IPC分类号： H01L23/544 ,  B28D5/00 ,  B44B7/00

    CPC分类号： H01L23/544 ,  B28D5/00 ,  H01L2223/54413 ,  H01L2223/54493 ,  H01L2924/0002 ,  H01L2924/00

    摘要： A semiconducting material substrate for use in integrated circuits manufacturing processes, where said substrate has a discoidal shape with two surfaces, i.e. a bottom surface and a top surface, respectively, and said substrate is also provided with marking indicia to indicate its crystallographic orientation. According to the present invention discoidal surfaces (2, 3; 12, 13) of said substrate (1; 11) have an axial symmetry and marking indicia (4, 5; 14) are executed at least on one of said discoidal surfaces (2, 3; 12, 13).

    摘要翻译： 用于集成电路制造工艺中使用，其中，所述基板具有圆盘形状具有两个表面，即半导体材料基板 因此底表面和顶表面，分别和所说基片上设置有标记标志，以指示其结晶取向。 。根据本发明的盘状表面（2,3; 12，13）所说基片（1; 11）具有在轴向对称和标记指示（4,5; 14）至少被执行在所述盘状表面中的一个（2 ，3; 12，13）。

    Non volatile memory structure and corresponding manufacturing process
    20.
    发明公开
    Non volatile memory structure and corresponding manufacturing process 失效
    NichtflüchtigeSpeicherstruktur und das entsprechende Herstellungsverfahren

    公开(公告)号：EP0977267A1

    公开(公告)日：2000-02-02

    申请号：EP98202563.7

    申请日：1998-07-30

    申请人： STMicroelectronics S.r.l.

    发明人： Dalla Libera, Giovanna ,  Pio, Federico

    IPC分类号： H01L27/115 ,  H01L29/788 ,  H01L21/8247 ,  H01L21/336

    CPC分类号： H01L29/42324 ,  H01L27/115

    摘要： The invention relates to non-volatile memory structure integrated on a semiconductor substrate and including a plurality of memory cells (1) each comprising a floating gate transistor having an active area (9) and source/drain (16, 17) regions as well as a control gate coupled to the floating gate, the floating gate transistor being serially connected to a selection transistor. According to the invention a contact (7) is provided on the control gate over the active area (9). The contact is substantially aligned to the central portion of the active area but may even be realized over double-poly wings (18, 19) of the gate region located asymmetrically with respect to the active area.

    摘要翻译： 本发明涉及集成在半导体衬底上并包括多个存储单元（1）的非易失性存储器结构，每个存储单元包括具有有源区（9）和源/漏（16,17）区的浮栅晶体管，以及 耦合到浮置栅极的控制栅极，所述浮栅晶体管串联连接到选择晶体管。 根据本发明，在有效区域（9）上的控制门上提供触点（7）。 接触件基本上对准有源区域的中心部分，但是甚至可以在相对于有源区域不对称地定位的栅极区域的双多面翼（18,19）上实现。