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    A METHOD FOR FORMING A SEMICONDUCTOR DEVICE
    13.
    发明公开
    A METHOD FOR FORMING A SEMICONDUCTOR DEVICE 审中-公开

    公开(公告)号：EP4391038A1

    公开(公告)日：2024-06-26

    申请号：EP22214882.7

    申请日：2022-12-20

    申请人： Imec VZW ,  Katholieke Universiteit Leuven KU Leuven Research & Development

    发明人： CHAN, Boon Teik ,  LIU, Hsiao-Hsuan ,  SCHUDDINCK, Pieter

    IPC分类号： H01L21/822 ,  H01L21/8238 ,  H01L27/06 ,  H01L27/092 ,  H01L29/06 ,  H01L29/775

    CPC分类号： H01L27/092 ,  H01L21/823871 ,  H01L21/823878 ,  H01L21/823842 ,  H01L21/823814 ,  H01L27/0688 ,  H01L21/8221 ,  H01L29/775 ,  H01L29/0673

    摘要： The disclosure relates to a method for forming a semiconductor device, comprising:
    forming, over a substrate, a stacked transistor structure comprising: a bottom channel structure and a top channel structure stacked on top of the bottom channel structure, a gate structure extending across the bottom and top channel structures, a first and a second bottom S/D structure on the bottom channel structure, and a first and a second top S/D structure on the top channel structure, wherein the first bottom and top S/D structures are formed at a first side of the gate structure, and the second bottom and top S/D structures are formed at a second side of the gate structure;
    forming a first and a second bottom S/D contact on the first and the second bottom S/D structures;
    forming a contact isolation layer capping the first and second bottom S/D contacts to form capped first and second bottom S/D contacts, and covering the capped first and second bottom S/D contacts with an ILD layer;
    forming a first contact trench exposing the first top S/D structure over the capped first bottom S/D contact;
    forming a second contact trench exposing the second bottom S/D contact and the second top S/D structure; and
    forming a first top S/D contact in the first contact trench, in contact with the first top S/D structure, over the capped first bottom S/D contact, and a second top S/D contact in the second contact trench, in contact with the second top S/D structure and the second bottom S/D contact.

    INTEGRATED CIRCUIT DEVICES COMPRISING BURIED POWER RAILS
    15.
    发明公开
    INTEGRATED CIRCUIT DEVICES COMPRISING BURIED POWER RAILS 审中-公开

    公开(公告)号：EP4391033A1

    公开(公告)日：2024-06-26

    申请号：EP22216344.6

    申请日：2022-12-23

    申请人： Imec VZW

    发明人： HIBLOT, Gaspard ,  CHAN, Boon Teik ,  MIRABELLI, Gioele

    IPC分类号： H01L21/768 ,  H01L23/528 ,  H01L23/535 ,  H01L29/775

    CPC分类号： H01L21/76897 ,  H01L23/5286 ,  H01L23/535 ,  H01L29/775 ,  H01L21/76831 ,  B82Y10/00 ,  H01L29/66439 ,  H01L29/0673 ,  H01L29/66545 ,  H01L29/42392 ,  H01L29/41725 ,  H01L27/088 ,  H01L21/823475 ,  H01L21/823481

    摘要： Method for forming an integrated circuit device (98), comprising: a. forming (901) a semiconductor device on a frontside (11) of a substrate (1) comprising: a device layer (2) on the frontside (11) of the substrate (1), the device layer (2) comprising a first active device (20), the substrate (1) comprising: shallow trench isolation structures (139, 131, 132, 133), wherein adjacent shallow trench isolation structures (139, 131, 132, 133) are separated from each other by a separating portion (1391, 1312, 1323) comprising the substrate material (100), a via (130) filled with a sacrificial plug (4) extending through the substrate material (100) in a first separating portion (1312), and wherein the sacrificial plug (4) contacts a source or drain contact (21) of the first active device (20), b. removing (902) the substrate material (100) from a backside of the substrate (1), c. depositing (903) a liner (9) covering the backside (10) of the substrate (1), d. anisotropically etching (904) the liner (9) so as to expose a first end (41) of the sacrificial plug (4), while retaining at least part of the liner (9) in the separating portions (1391, 1312, 1323), e. removing (905) the sacrificial plug (4) selectively with respect to the liner (9), and f. providing (906) an electrically conductive material (30) in the via (130), electrically coupled to a buried power rail (31, 32).

    VERFAHREN ZUR HERSTELLUNG EINER PLANEN FREIEN KONTAKTIERFLÄCHE FÜR HALBLEITERNANOSTRUKTUREN
    19.
    发明公开
    VERFAHREN ZUR HERSTELLUNG EINER PLANEN FREIEN KONTAKTIERFLÄCHE FÜR HALBLEITERNANOSTRUKTUREN 审中-公开

    公开(公告)号：EP3384533A1

    公开(公告)日：2018-10-10

    申请号：EP16798073.9

    申请日：2016-10-22

    申请人： Forschungszentrum Jülich GmbH

    发明人： HEEDT, Sebastian ,  GERHARZ, Julian ,  SCHÄPERS, Thomas ,  GRÜTZMACHER, Detlev

    IPC分类号： H01L29/66 ,  H01L29/06 ,  H01L29/40 ,  H01L29/775 ,  B82Y10/00 ,  B82Y40/00

    CPC分类号： H01L29/0673 ,  B82Y10/00 ,  B82Y40/00 ,  H01L29/401 ,  H01L29/66469 ,  H01L29/775

    摘要： The invention relates to a method for producing a flat free contacting surface for semiconductor nanostructures, wherein at least one nanostructure (2) is arranged on the surface of a transfer substrate (1). A first layer (3) in which at least one nanostructure (2) is embedded is applied onto the same surface of the transfer substrate (1), and a second substrate (5) is applied onto the first layer (3). The transfer substrate (1) is then separated from the first layer (3) such that the at least one nanostructure (2) embedded in the first layer has a flat free surface. According to the invention, prior to applying the at least one nanostructure (2) onto the transfer substrate (1), an additional layer (6) which can be removed by means of a solvent is applied onto the surface of the transfer substrate (1), and the transfer substrate (1) is removed from the first layer (3) using a solvent. In this manner, a planarization/layering of nanostructures and a subsequent simplified electric contacting process is allowed. When the method steps are applied in iterations, multilayers can be constructed advantageously from horizontally aligned nanowire networks for example (figure 5B).