公开(公告)号：EP2120059A4

公开(公告)日：2014-01-08

申请号：EP08721973

申请日：2008-03-06

申请人： NEC CORP ,  RENESAS ELECTRONICS CORP ,  HANWA ELECTRONIC IND CO LTD

发明人： TSUKAGOSHI TSUNEO ,  WATANABE TAKESHI ,  NAKAIE TOSHIYUKI ,  MATSUI NOBUCHIKA

IPC分类号： G01R31/30 ,  G01R31/00 ,  G01R31/28

CPC分类号： G01R31/002 ,  G01R31/2841 ,  G01R31/3004

公开(公告)号：EP2378776A4

公开(公告)日：2013-10-16

申请号：EP09838201

申请日：2009-01-15

申请人： RENESAS ELECTRONICS CORP

发明人： MOCHIZUKI SEIJI ,  FUNABASHI YUTAKA ,  KIMURA JUNICHI ,  EHAMA MASAKAZU

IPC分类号： H04N19/51 ,  H04N19/11 ,  H04N19/134 ,  H04N19/139 ,  H04N19/176 ,  H04N19/196 ,  H04N19/44 ,  H04N19/46 ,  H04N19/50 ,  H04N19/513 ,  H04N19/59 ,  H04N19/593 ,  H04N19/70

CPC分类号： H04N19/11 ,  H04N19/44 ,  H04N19/583 ,  H04N19/593 ,  H04N19/61

摘要： Adopted is a decoder, in which on condition that a prediction block shown by vector information extracted from a data stream, and a decode-target block have an overlap where respective pixels overlay each other, pixel information of an already-decoded portion at a distance of an integer multiple of a vector provided by the vector information from the overlap is made a prediction signal instead of the overlap, and the prediction signal is added to difference image data taken from the data stream to generate reproduction image data. The decoder is adopted for an intra-frame decoder, a local decoder of an encoder, and the like. According to a fundamental rule concerning a repetitive pattern of an image, a pixel at a distance of an integer multiple is a like pixel, and therefore the process of decoding can be performed efficiently.

公开(公告)号：EP2284874A4

公开(公告)日：2012-12-19

申请号：EP09754429

申请日：2009-05-26

申请人： RENESAS ELECTRONICS CORP ,  ULVAC INC

发明人： KINOSHITA KEIZO ,  CHIKAKI SHINICHI ,  NAKAYAMA TAKAHIRO

IPC分类号： H01L21/312 ,  H01L21/3105 ,  H01L21/768 ,  H01L23/522 ,  H01L23/532

CPC分类号： H01L23/5329 ,  H01L21/02126 ,  H01L21/02203 ,  H01L21/3105 ,  H01L21/76814 ,  H01L21/7682 ,  H01L21/76826 ,  H01L23/53295 ,  H01L2221/1047 ,  H01L2924/0002 ,  H01L2924/12044 ,  H01L2924/00

公开(公告)号：EP2541829A4

公开(公告)日：2017-04-12

申请号：EP11747311

申请日：2011-02-22

申请人： RENESAS ELECTRONICS CORP

发明人： NAGANUMA KEN ,  OWADA TORU ,  ANDO ERIKO

IPC分类号： H04L9/14 ,  G06F21/35 ,  G06F21/74 ,  H04L9/32 ,  H04L29/06 ,  H04W12/06

CPC分类号： H04L9/3242 ,  G06F21/35 ,  G06F21/74 ,  G06F2221/2105 ,  H04L63/08 ,  H04L63/0838 ,  H04L63/0869 ,  H04L63/123 ,  H04L2209/80 ,  H04L2209/84 ,  H04W12/06

摘要： An authentication method is provided which is capable of performing message authentication within an allowable time regardless of the magnitude of the number of messages and performing message authentication high in accuracy within a range for which the allowable time allows. Upon transmission by wireless communications with another mobile or a fixed station, a message authentication code of communication data and a digital signature are generated (S200 and S300). The generated message authentication cod and digital signature are transmitted with being added to the communication data. Upon reception, whether authentication should be done using either one of the message authentication code and the digital signature included in received information is determined according to its own state for the authentication (S400 and S500). This state includes, for example, a load state of a central processing unit or the like that performs an authentication process.

公开(公告)号：EP3032540A4

公开(公告)日：2017-03-15

申请号：EP13891121

申请日：2013-08-06

申请人： RENESAS ELECTRONICS CORP

发明人： NII KOJI

IPC分类号： H01L27/11 ,  G11C8/16 ,  G11C11/412 ,  H01L27/02

CPC分类号： H01L27/1104 ,  G11C8/16 ,  G11C11/412 ,  G11C11/417 ,  H01L23/528 ,  H01L27/0207 ,  H01L27/1116 ,  H01L29/1095 ,  H01L29/41758 ,  H01L29/7851 ,  H01L2924/0002 ,  H01L2924/00

摘要： In a chip that processes image information or the like, a multi-port SRAM is mixed together with a logic circuit such as a digital signal processing circuit. In that case, for example, in case that the 3 port is used, the 1 port may serve as a differential write and readout port, and the 2 port may serve as a single ended readout dedicated port. However, in this configuration, it is obvious that there is a problem, in that while the occupied area of an embedded SRAM is reduced, the number of write and readout ports is limited to only one, and readout characteristics as fast as differential readout cannot be expected in single ended readout. The outline of the present application is that three differential write and readout ports are included in a memory cell structure of the embedded SRAM, an N-well region, for example, is arranged at the center of a cell, and a P-well region is arranged on both sides thereof.

摘要翻译： 在处理图像信息等的芯片中，多端口SRAM与诸如数字信号处理电路的逻辑电路混合在一起。 在这种情况下，例如，在使用3端口的情况下，1端口可以用作差分写入和读出端口，并且2端口可以用作单端读出专用端口。 然而，在这种配置中，显然存在一个问题，即当嵌入式SRAM的占用面积减小时，写入和读出端口的数量仅限于一个，并且与差分读出一样快的读出特性不能 预计在单端读出。 本申请的概述是三个差分写入和读出端口包括在嵌入式SRAM的存储单元结构中，例如，N阱区域被布置在单元的中心，并且P阱区域 布置在其两侧。

公开(公告)号：EP2894757A4

公开(公告)日：2016-06-29

申请号：EP13835877

申请日：2013-06-19

申请人： RENESAS ELECTRONICS CORP

发明人： ICHIKAWA KATSUEI

IPC分类号： H02J7/00 ,  H01F38/14 ,  H01M10/46

CPC分类号： H02J7/025 ,  H01M10/46 ,  H02J7/0042 ,  H02J17/00 ,  H02J50/12 ,  H02J50/70 ,  H02J50/80 ,  H02J50/90 ,  H02J2007/0096 ,  H04B5/0037

摘要： A wide charging area and communication area are ensured in a non-contact power supply system with wireless communication. The present invention includes a resonance coil, a wireless communication antenna coil, a power supply coil, and a sensitivity adjustment circuit coupled to the power supply coil. When electric power is supplied in a contactless manner, the power supply coil and the resonance coil are coupled electromagnetically and electric power supply from the resonance coil is performed by using a magnetic resonance method. When wireless communication is performed, the magnetic fluxes of the wireless communication antenna coil are coupled with those of the resonance coil and sensitivity is enhanced by the sensitivity adjustment circuit.

公开(公告)号：EP2882104A4

公开(公告)日：2016-05-25

申请号：EP12882294

申请日：2012-08-01

申请人： RENESAS ELECTRONICS CORP

发明人： KAWASAKI YOICHI

IPC分类号： H03K19/0185 ,  G11C16/08 ,  G11C16/12 ,  G11C16/14 ,  G11C16/30 ,  H03K3/356

CPC分类号： H03K19/018521 ,  G11C16/08 ,  G11C16/12 ,  G11C16/14 ,  G11C16/30 ,  H03K3/356104 ,  H03K3/35613

摘要： A level shift circuit includes: a latch circuit (Q5, Q6, Q7, Q8) including first (Q5, Q7) and second (Q6, Q8) inverter circuits; a first input MOS transistor (Q1) operating in accordance with an input signal; a second input MOS transistor (Q2) operating in accordance with an inversion signal of the input signal; and a current-voltage control MOS transistor (Q9). The latch circuit (Q5, Q6, Q7, Q8) outputs a voltage having been converted from the input voltage in level. Each of the first and second input MOS transistors (Q1, Q2) receives the input signal at its gate terminal, and drives the latch circuit (Q5, Q6, Q7, Q8) in accordance with the input signal. The current-voltage control MOS transistor (Q9) is provided between the input MOS transistor (Q1, Q2) and the latch circuit (Q5, Q6, Q7, Q8), and is driven in accordance with an inversion operation of the latch circuit by receiving an input of the control voltage at its gate terminal.

公开(公告)号：EP2541604A4

公开(公告)日：2016-04-20

申请号：EP10846515

申请日：2010-02-25

申请人： RENESAS ELECTRONICS CORP

发明人： ARAI DAISUKE ,  NAKAZAWA YOSHITO ,  HOSOYA NORIO

IPC分类号： H01L29/739 ,  H01L21/336 ,  H01L29/06 ,  H01L29/12 ,  H01L29/40 ,  H01L29/66 ,  H01L29/78 ,  H01L29/786

CPC分类号： H01L29/7395 ,  H01L24/05 ,  H01L29/0653 ,  H01L29/0696 ,  H01L29/402 ,  H01L29/66333 ,  H01L2224/04042 ,  H01L2224/45144 ,  H01L2224/48463 ,  H01L2224/73265 ,  H01L2924/13055 ,  H01L2924/14 ,  H01L2924/00

公开(公告)号：EP2892054A4

公开(公告)日：2016-03-30

申请号：EP12883828

申请日：2012-08-29

申请人： RENESAS ELECTRONICS CORP

发明人： OGAWA TOMOYA ,  ITO TAKASHI ,  TOMOEDA MITSUHIRO

IPC分类号： G11C16/06 ,  G11C16/02 ,  G11C16/14

CPC分类号： G11C16/14 ,  G11C16/06 ,  G11C16/12 ,  G11C16/30 ,  G11C16/32

摘要： In a nonvolatile memory device (4) provided in a semiconductor device, when data is erased based on a band-to-band tunneling scheme, supply of a boosted voltage to a memory cell (MC) to be erased is ended when a condition that an output voltage (VUCP) of a charge pump circuit (52) has recovered to a predetermined reference voltage is satisfied and additionally a condition that a predetermined reference time has elapsed since start of supply of the boosted voltage (VUCP) to the memory cell (MC) to be erased is satisfied.

公开(公告)号：EP2799997A4

公开(公告)日：2015-12-09

申请号：EP11878346

申请日：2011-12-26

申请人： RENESAS ELECTRONICS CORP

发明人： YU THOMAS EDISON CHUA ,  YAMASHITA HAJIME ,  ITO MASAYUKI

IPC分类号： G06F12/08 ,  G06F11/10 ,  G06F12/12

CPC分类号： G06F12/0864 ,  G06F11/1064 ,  G06F12/126 ,  G06F12/127 ,  G06F2212/1028 ,  G06F2212/6032 ,  Y02B60/1225 ,  Y02D10/13

摘要： Part of a plurality of ways are selected from among the ways according to a value of select data created based on tag address information which is part of address information, and cache tags are read. Further, when performing cache fill, the cache memory performs the cache fill on a cache entry selected from part of the ways according to the value of the select data. For select data used for selecting a way, e.g. parity data in connection with tag address information is used. A way to read a cache tag from is selected based on a value of parity data and further, the way of a cache entry to perform cache fill on is selected.