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53 条记录 (耗时 0.012 秒)

    METHOD FOR REMOVING RESIDUES WITH REDUCED ETCHING OF OXIDE
    32.
    发明公开
    METHOD FOR REMOVING RESIDUES WITH REDUCED ETCHING OF OXIDE 审中-公开
    与降低处置废物的方法，通过蚀刻氧化物

    公开(公告)号：EP1171908A1

    公开(公告)日：2002-01-16

    申请号：EP01906565.5

    申请日：2001-01-17

    申请人： Philips Semiconductors Inc. ,  Koninklijke Philips Electronics N.V.

    发明人： YEH, Edward, K. ,  GABRIEL, Calvin, Todd ,  ZHENG, Tammy ,  LEARD, Linda

    IPC分类号： H01L21/3213 ,  G03F7/42

    CPC分类号： H01L21/02071 ,  G03F7/427

    摘要： A method for removing plasma etching-induced residues. In one embodiment, after a portion of photoresist has been used to form a polysilicon gate, the present invention provides a novel and advantageous plasma ashing environment. Specifically, in this embodiment, the present invention introduces CF4 into the plasma ashing environment. Next, the present embodiment introduces H20 vapor into the plasma ashing environment. In this embodiment, the ratio by volume of the CF4 to the H20 is in the range of from 0.1:1 to 10:1. Next, the present embodiment uses the plasma ashing environment to substantially remove polysilicon etch-induced residues without requiring an aggressive chemical strip. In so doing, the etching of the gate oxide is significantly suppressed such that a sufficient amount of the gate oxide layer remains above the underlying semiconductor substrate. Additionally, in the present invention, after the removal of the plasma etching-induced residues, the gate oxide layer is clean and enough gate oxide remains such that the thickness of the remaining gate oxide layer can be accurately and reliably measured.

    METHOD FOR DETERMINING ROTATIONAL ERROR PORTION OF TOTAL MISALIGNMENT ERROR IN A STEPPER
    34.
    发明公开
    METHOD FOR DETERMINING ROTATIONAL ERROR PORTION OF TOTAL MISALIGNMENT ERROR IN A STEPPER 审中-公开
    PROCEDURE用于确定总对准误差的旋转误差百分比在步进机

    公开(公告)号：EP1145081A1

    公开(公告)日：2001-10-17

    申请号：EP00965211.6

    申请日：2000-09-20

    申请人： Koninklijke Philips Electronics N.V. ,  Philips Semiconductors Inc.

    发明人： LEROUX, Pierre

    IPC分类号： G03F7/20

    CPC分类号： G03F7/70591 ,  G03F7/70633

    摘要： A method for determining rotational error portion of total misalignment error in a stepper. In one embodiment, the method comprises a series of steps in a stepper, starting with the step of receiving a wafer, having a first pattern and an error-free fine alignment target, in the stepper. In another step, the wafer is aligned in the stepper using the error-free fine alignment target. Then a second pattern is created on the wafer overlaying said first pattern. In another step, the rotational error portion of the total misalignment error is determined by measuring the circumferential misalignment between the first pattern and the second pattern.

    INTEGRATED-CIRCUIT MANUFACTURING USING HIGH INTERSTITIAL-RECOMBINATION-RATE BLOCKING LAYER FOR SOURCE/DRAIN EXTENSION IMPLANT
    36.
    发明公开
    INTEGRATED-CIRCUIT MANUFACTURING USING HIGH INTERSTITIAL-RECOMBINATION-RATE BLOCKING LAYER FOR SOURCE/DRAIN EXTENSION IMPLANT 审中-公开
    方法用于集成电路USING A阻挡层用于植入高的间隙的复合率源极/漏极延伸

    公开(公告)号：EP1138074A1

    公开(公告)日：2001-10-04

    申请号：EP00957940.0

    申请日：2000-09-01

    申请人： Koninklijke Philips Electronics N.V. ,  Philips Semiconductors Inc.

    发明人： RUBIN, Mark, E.

    IPC分类号： H01L21/8238 ,  H01L21/265 ,  H01L21/336

    CPC分类号： H01L29/6659 ,  H01L21/2652 ,  H01L21/823814 ,  H01L29/6656

    摘要： In the fabrication of a 0.10 micron CMOS integrated circuit (IC), a high-energy plasma etch is used to pattern a polysilicon layer (25) and an underlying gate oxide layer (23) to define gate structures. A thermal oxide step (S2) anneals silicon exposed and damaged by this etch. Instead of using this thermal oxide as a blocking layer for a source/drain extension implant, it is removed (S3) so as to expose the silicon surfaces of the source/drain regions. A TEOS deposition (S4) results in a carbon-bearing silicon dioxide layer (51) in contact with the surfaces of the crystalline source/drain regions. A boron PMOS source/drain extension implant (S5) is performed through this carbon-bearing blocking layer. Subsequent steps (S6-S9) result in the formation of sidewall spacers (71), heavily doped deep source/drain sections (91, 93), submetal dielectric (81), an intermetal dielectric interconnect structure, and passivation. The relatively high interstitial recombination rate of the carbon-bearing blocking layer attracts a flow of interstitial silicon. This flow draws some of the boron extension implant with it - effectively limiting the depth and lateral extension (under the gate) of the boron. This, in turn, helps limit the short-channel effect, and yields a more reliable 0.1 micron PMOS transistor.

    MULTI-MODE DIRECT MEMORY ACCESS CONTROLLER AND METHOD
    38.
    发明授权
    MULTI-MODE DIRECT MEMORY ACCESS CONTROLLER AND METHOD 有权
    多重模式直接存储器访问控制和程序

    公开(公告)号：EP1295210B1

    公开(公告)日：2006-06-14

    申请号：EP01944419.9

    申请日：2001-06-11

    申请人： Philips Semiconductors Inc. ,  Koninklijke Philips Electronics N.V.

    发明人： STORY, Franklyn, H. ,  MEIYAPPAN, Subramanian, S.

    IPC分类号： G06F13/28

    CPC分类号： G06F13/364 ,  G06F13/28 ,  Y02D10/14

    摘要： A novel and sophisticated direct memory access (DMA) controller that can operate in either "fly-by" mode, "dual-cycle" mode, or "flow-through" mode. The DMA controller of the present embodiment supports a parametrizable number of channels, each of the channels providing support for one of the prior-noted modes of operation. The DMA controller of the present embodiment serves as bus master on the host bus and has the ability to interface with all the devices on the system. The DMA controller of the present embodiment is also optimized for zero wait state sequential transfers on the host bus. Further, the DMA controller of the present embodiment also houses an internal arbiter with programmable priority to choose arbitrate between the different channels, should more than one master that interface to the DMA controller request access to the host bus. An advantage of the present invention is that, because bus master devices are be off-loaded from the host bus, system performance can be dramatically improved. Another advantage is that the present invention provides an easy means for adding more devices to the system.

    Synchronization device and method
    40.
    发明公开
    Synchronization device and method 审中-公开
    同步的装置和方法

    公开(公告)号：EP0946016A3

    公开(公告)日：2002-06-05

    申请号：EP99302234.2

    申请日：1999-03-23

    申请人： Philips Semiconductors Inc.

    发明人： Ott, Stefan

    IPC分类号： H04L7/02 ,  H03L7/07 ,  H03L7/095

    CPC分类号： H03L7/199 ,  H03L7/095 ,  H04L7/0012

    摘要： A clock synchronization circuit for synchronizing a first communications device and a second communications device to enable digital communication between the devices. The clock synchronization circuit includes an oscillator circuit adapted to generate a base clock signal. A first frequency divider is coupled to the oscillator circuit. The first frequency divider generates a first divider clock signal from the base clock signal. A phase comparison circuit is coupled to receive the first divider clock signal. Additionally, the phase comparison circuit is also coupled to the oscillator circuit to control the frequency of the base clock signal. The phase comparison circuit receives a reference clock signal from a first communications device and adjusts the base clock frequency to correct a phase difference between the first divider clock signal and the reference clock signal. The clock synchronization circuit further includes a second frequency divider coupled to the oscillator circuit. The second frequency divider is adapted to generate a second divider clock signal from the base clock signal, wherein the second divider clock signal varies in response to the correcting performed on the base clock signal by the phase comparison circuit. The second frequency divider subsequently provides the second divider clock signal to a second communications device such that the first communications device and the second communications device are synchronized.