公开(公告)号：EP2338169A1

公开(公告)日：2011-06-29

申请号：EP09813382.0

申请日：2009-01-07

申请人： LSI Corporation

发明人： LOW, Qwai, H. ,  GUO, Chengyu

IPC分类号： H01L23/055

CPC分类号： H01L23/49816 ,  H01L23/3128 ,  H01L23/481 ,  H01L23/49838 ,  H01L24/29 ,  H01L24/32 ,  H01L24/48 ,  H01L24/73 ,  H01L2224/13099 ,  H01L2224/2929 ,  H01L2224/32225 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/484 ,  H01L2224/73257 ,  H01L2224/73265 ,  H01L2224/83194 ,  H01L2224/92125 ,  H01L2924/00014 ,  H01L2924/00015 ,  H01L2924/01014 ,  H01L2924/01023 ,  H01L2924/01031 ,  H01L2924/01032 ,  H01L2924/01033 ,  H01L2924/01057 ,  H01L2924/01082 ,  H01L2924/07811 ,  H01L2924/10252 ,  H01L2924/10253 ,  H01L2924/10329 ,  H01L2924/12041 ,  H01L2924/14 ,  H01L2924/15311 ,  H01L2924/15312 ,  H01L2924/181 ,  H01L2224/48233 ,  H01L2224/45099 ,  H01L2924/0665 ,  H01L2924/00 ,  H01L2924/00012

摘要： A wire bond design integrated circuit with a substrate having a front side and an opposing back side. Circuitry is disposed on the font side. Electrically conductive vias are disposed through the substrate from the front side to the back side, and are electrically connected to the circuitry such that the electrically conductive vias provide power and ground services only for the circuitry. Bonding pads are disposed on the front side, and are electrically connected to the circuitry such that the bonding pads provide signal communication only for the circuitry.

公开(公告)号：EP2130221A1

公开(公告)日：2009-12-09

申请号：EP07852471.7

申请日：2007-09-27

申请人： LSI Corporation

发明人： FISHLEY, Clifford ,  AWUJOOLA, Abiola ,  MORA, Leonard ,  AMIN, Amar ,  OTHIENO, Maurice ,  CHIA, Chok J.

IPC分类号： H01L23/28

CPC分类号： H01L23/66 ,  H01L23/49838 ,  H01L23/50 ,  H01L24/45 ,  H01L24/48 ,  H01L2224/451 ,  H01L2224/45147 ,  H01L2224/48233 ,  H01L2924/00014 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/14 ,  H01L2924/30107 ,  H01L2924/3011 ,  H01L2924/3025 ,  H01L2924/00015 ,  H01L2224/05599

摘要： An integrated circuit package includes a package substrate, a die attach pad formed on the package substrate for securing a die to the package substrate, a ground bonding ring formed on the package substrate for attaching core and I/O ground bond wires between the die and the package substrate, and a first plurality of bond fingers formed immediately adjacent to the ground bonding ring for attaching a first set of I/O signal bond wires between the package substrate and the die.

摘要翻译： 一种集成电路封装，包括封装基板，形成在封装基板上的管芯安装焊盘，用于将管芯固定到封装基板;形成在封装基板上的接地环，用于将芯和I / O接地线连接在管芯和管芯之间; 所述封装基板和紧邻所述接地环形成的第一多个接合指，用于在所述封装基板和所述管芯之间附接第一组I / O信号接合线。

公开(公告)号：EP0903780A2

公开(公告)日：1999-03-24

申请号：EP98116369.4

申请日：1998-08-28

申请人： Texas Instruments Incorporated

发明人： Orcutt, John W.

IPC分类号： H01L21/60 ,  H01L23/49

CPC分类号： H01L24/85 ,  H01L23/49816 ,  H01L23/50 ,  H01L24/45 ,  H01L24/48 ,  H01L24/49 ,  H01L2224/05554 ,  H01L2224/45015 ,  H01L2224/45124 ,  H01L2224/45139 ,  H01L2224/45144 ,  H01L2224/45147 ,  H01L2224/48091 ,  H01L2224/48095 ,  H01L2224/48227 ,  H01L2224/48233 ,  H01L2224/48465 ,  H01L2224/4848 ,  H01L2224/48599 ,  H01L2224/48624 ,  H01L2224/48644 ,  H01L2224/48647 ,  H01L2224/48699 ,  H01L2224/48724 ,  H01L2224/48744 ,  H01L2224/48747 ,  H01L2224/48824 ,  H01L2224/48844 ,  H01L2224/48847 ,  H01L2224/49171 ,  H01L2224/8503 ,  H01L2224/85051 ,  H01L2224/85148 ,  H01L2224/85205 ,  H01L2224/85424 ,  H01L2224/85444 ,  H01L2224/85447 ,  H01L2924/00014 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01029 ,  H01L2924/01047 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/09701 ,  H01L2924/10162 ,  H01L2924/14 ,  H01L2924/1433 ,  H01L2924/15153 ,  H01L2924/15165 ,  H01L2924/1517 ,  H01L2924/15311 ,  H01L2924/1532 ,  H01L2924/181 ,  H01L2224/78 ,  H01L2924/00 ,  H01L2924/00012

摘要： An integrated circuit in a package having a ground(13) and/or power ring (16) and bond wires (19) crossing the ground and/or power ring, the bond wires further coupled to signal traces (21). A semiconductor integrated circuit (17) is provided in a die cavity (12) in a substrate. Signal traces are formed on the surface of the substrate (11). At least one conductive area is formed surrounding the die cavity. At least one signal trace is formed on the substrate and electrically isolated from the conductive ring. Bond wires are used to couple the die bond pads (21) to the signal traces. At least some of the bond wires are coupled to signal traces and must cross the conductive ring. The bond wires are raised a clearance distance over the power or ground ring by forming a spacer (24) on the inner end of the signal traces. The spacer formed on the signal trace then provides a clearance spacing to prevent the bond wires which cross the power ring from becoming shorted to the power ring. Typically, the spacer is formed as a bond wire ball placed on the signal trace. Typically the conductive ring is used as a ground ring, or as a voltage supply ring, for the integrated circuit. Multiple power or ground rings are used in some embodiments. Other devices and methods are described.

摘要翻译： 封装中的集成电路具有接地（13）和/或功率环（16）以及与接地和/或功率环交叉的接合线（19），接合线还耦合到信号迹线（21）。 半导体集成电路（17）设置在衬底中的模腔（12）中。 信号迹线形成在衬底（11）的表面上。 围绕模腔形成至少一个导电区域。 至少一个信号迹线形成在衬底上并与导电环电隔离。 键合线用于将管芯键合焊盘（21）耦合到信号迹线。 至少一些键合线被耦合到信号迹线并且必须穿过导电环。 通过在信号迹线的内端形成间隔物（24），键合线在电源或接地环上升高间隙距离。 形成在信号迹线上的隔离物然后提供间隙空间以防止穿过电源环的键合线与电源环短路。 典型地，间隔物形成为放置在信号迹线上的接合线球。 通常，导电环用作集成电路的接地环或电压供应环。 在一些实施例中使用多个电源或接地环。 描述了其他设备和方法。

公开(公告)号：EP0415318A3

公开(公告)日：1992-05-27

申请号：EP90116385.7

申请日：1990-08-27

申请人： SUMITOMO ELECTRIC INDUSTRIES, LTD.

发明人： Shiga, Nobuo, c/o Yokohama Works

IPC分类号： H01L23/64 ,  H03F3/08 ,  H04B10/14

CPC分类号： H01L23/642 ,  H01L24/48 ,  H01L24/49 ,  H01L2224/48233 ,  H01L2224/48237 ,  H01L2224/49171 ,  H01L2924/00014 ,  H01L2924/01019 ,  H01L2924/01046 ,  H01L2924/01079 ,  H01L2924/12043 ,  H01L2924/14 ,  H01L2924/19041 ,  Y10S257/916 ,  H01L2224/45099 ,  H01L2224/05599 ,  H01L2924/00

摘要： The invention concerns a semiconductor device comprising a semiconductor chip (15) having a reception circuit for removing a direct-current component of a reception signal by the utilization of a capacitor and a metal film formed on the back side thereof; a first conductive pattern (12) formed on an electrically insulating substrate (11) and set at a common reference voltage for device; and a second conductive pattern (13) formed on said substrate (11) to be electrically insulated from said first conductive pattern (12), fixed to said metal film, and electrically connected to said capacitor. This arrangement results in a high receiving sensitivity and a wide receiving band of the reception circuit, because there is almost no floating capacitance present in the capacitor.

公开(公告)号：EP0416726A3

公开(公告)日：1991-06-26

申请号：EP90307624.8

申请日：1990-07-12

申请人： ADVANCED MICRO DEVICES, INC.

发明人： Chu, George Dongwoo

IPC分类号： H01L23/495

CPC分类号： H01L24/49 ,  H01L23/4334 ,  H01L23/49527 ,  H01L23/49811 ,  H01L23/50 ,  H01L23/66 ,  H01L24/45 ,  H01L24/48 ,  H01L2224/05554 ,  H01L2224/45144 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/48233 ,  H01L2224/48247 ,  H01L2224/48253 ,  H01L2224/49109 ,  H01L2224/4911 ,  H01L2224/49171 ,  H01L2224/73265 ,  H01L2924/00014 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01015 ,  H01L2924/01029 ,  H01L2924/01075 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/14 ,  H01L2924/15153 ,  H01L2924/1517 ,  H01L2924/15787 ,  H01L2924/19041 ,  H01L2924/19107 ,  H01L2924/30107 ,  H01L2924/3011 ,  H01L2924/00 ,  H01L2224/05599

摘要： A high performance plastic-encapsulated integrated circuit package is disclosed having both improved heat dissipation and low ground noise comprising one or more separate ground and/or power planes below the signal lines which includes an electrically conductive heat sink member (20) on which an integrated circuit die (10) is centrally mounted for dissipating heat and which may also may function as a ground or power plane, a peripheral printed circuit board (30) having electrically conductive members formed on one or more surfaces thereof, one surface of which is also mounted to the heat sink and electrically separated therefrom and which surrounds the centrally mounted die on the heat sink, and a lead frame assembly (70) bonded to an opposite surface of the printed circuit board. Terminal pads on the die are connected respectively to leads on the lead frame, to the electrically conductive members on the printed circuit board, and to the electrically conductive heat sink. Terminal pads (42) on one surface of the printed circuit board may be used in combination with electrically conductive vias (46a,46b) to provide electrical connection to the other surface of the printed circuit board as well as to the electrically conductive heat sink.

公开(公告)号：EP0072644A2

公开(公告)日：1983-02-23

申请号：EP82304063.9

申请日：1982-08-02

申请人： AMP INCORPORATED (a New Jersey corporation)

发明人： Grabbe, Dimitry G.

IPC分类号： H01L23/56

CPC分类号： H01L24/49 ,  H01L23/647 ,  H01L24/48 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/48233 ,  H01L2224/48465 ,  H01L2224/49 ,  H01L2924/00014 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01029 ,  H01L2924/01082 ,  H01L2924/12042 ,  H01L2924/14 ,  H01L2924/15173 ,  H01L2924/15747 ,  H01L2924/15787 ,  H01L2924/19041 ,  H01L2924/19043 ,  H01L2924/3011 ,  H01L2924/00 ,  H01L2224/45099 ,  H01L2224/05599

摘要： Chip carrier comprises a plurality of copper leads (14,19, 23) bonded to a ceramic substrate (10) and extending from the edges (17) thereof toward the center where a ground bus (18) and a power bus (22) surround a conductive mounting pad (12) for a semiconductor chip (13). Each bus (18, 22) is preferably connected to a single lead (19, 23) and is provided with a pad (20, 24) for mounting a decoupling capacitor in close proximity to the chip (13) to assure low reactance due to switching. Resistive material (26) may be deposited between the signal leads (14) and the ground bus (18) for laser trimming to selectively disconnect signal leads (14) from the ground bus (18), or to create separate resistor paths (28) for each signal lead (14) to bus (18) while trimming the resistor (28) to the required transmission line terminating value.

摘要翻译： 芯片载体包括多个接合到陶瓷基板（10）并从其边缘（17）延伸到接地总线（18）和电源总线（22）的中心的铜引线（14,19,23） 用于半导体芯片（13）的导电安装垫（12）。 每个总线（18,22）优选地连接到单个引线（19,23），并且设置有用于安装非常靠近芯片（13）的去耦电容器的焊盘（20,24），以确保由于 交换。 电阻材料（26）可以沉积在信号引线（14）和接地总线（18）之间用于激光微调以选择性地将信号引线（14）与接地总线（18）断开，或者产生分离的电阻器通路（28） 对于每个信号引线（14）到总线（18），同时将电阻器（28）调整到所需的传输线终端值。

公开(公告)号：EP2130221B1

公开(公告)日：2017-11-08

申请号：EP07852471.7

申请日：2007-09-27

申请人： LSI Corporation

发明人： FISHLEY, Clifford ,  AWUJOOLA, Abiola ,  MORA, Leonard ,  AMIN, Amar ,  OTHIENO, Maurice ,  CHIA, Chok J.

IPC分类号： H01L23/28 ,  H01L23/498 ,  H01L23/50 ,  H01L23/66 ,  H01L23/00

CPC分类号： H01L23/66 ,  H01L23/49838 ,  H01L23/50 ,  H01L24/45 ,  H01L24/48 ,  H01L2224/451 ,  H01L2224/45147 ,  H01L2224/48233 ,  H01L2924/00014 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/14 ,  H01L2924/30107 ,  H01L2924/3011 ,  H01L2924/3025 ,  H01L2924/00015 ,  H01L2224/05599

公开(公告)号：EP1573812A1

公开(公告)日：2005-09-14

申请号：EP03777036.9

申请日：2003-12-04

申请人： Koninklijke Philips Electronics N.V.

发明人： WYLAND, Chris

IPC分类号： H01L23/64 ,  H01L23/498

CPC分类号： H01L24/85 ,  H01L23/49811 ,  H01L23/49816 ,  H01L23/50 ,  H01L23/585 ,  H01L23/645 ,  H01L23/66 ,  H01L24/37 ,  H01L24/40 ,  H01L24/45 ,  H01L24/48 ,  H01L24/49 ,  H01L24/73 ,  H01L24/84 ,  H01L24/91 ,  H01L2223/6611 ,  H01L2224/05554 ,  H01L2224/05644 ,  H01L2224/37147 ,  H01L2224/40225 ,  H01L2224/45015 ,  H01L2224/48011 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/48233 ,  H01L2224/484 ,  H01L2224/49 ,  H01L2224/73221 ,  H01L2224/73229 ,  H01L2224/85 ,  H01L2224/92 ,  H01L2924/00014 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01014 ,  H01L2924/01015 ,  H01L2924/01023 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01047 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/14 ,  H01L2924/20752 ,  H01L2924/30107 ,  H01L2924/3011 ,  H01L2224/83 ,  H01L2224/84 ,  H01L2924/20655 ,  H01L2224/78 ,  H01L2924/00 ,  H01L2224/45099

摘要： One aspect of the present invention relates to reducing the impedance of the paths connecting the power or ground of a device and a BGA package. In a particular example implementation, impedance of the signal bond wires is controlled by placing a ground strap ( 130 ) at a predetermined distance from the signal bond wires ( 115 ). In a related example embodiment, a low impedance power or ground connection is made between a device die ( 140 ) and package in close proximity to wire bonds ( 115 ). An integrated circuit ( 140 ) includes a plurality of grounding pads, signal pads, power pads and a package for mounting the integrated circuit. The package ( 100 ) comprises a plurality of pad landings ( 110 ), a grounding ring ( 105 ) surrounding the integrated circuit ( 140 ); and a grounding strap ( 130 ) coupling the grounding ring ( 105 ) to the grounding pads ( 120 ) of the integrated circuit.

公开(公告)号：EP0902471A3

公开(公告)日：1999-11-03

申请号：EP98306868.5

申请日：1998-08-27

申请人： Oki Electric Industry Company, Limited

发明人： Kohara, Youichi ,  Oka, Takahiro

IPC分类号： H01L23/485 ,  H01L23/13

CPC分类号： H01L24/06 ,  H01L23/50 ,  H01L23/552 ,  H01L24/05 ,  H01L24/48 ,  H01L24/49 ,  H01L2223/6611 ,  H01L2224/04042 ,  H01L2224/05554 ,  H01L2224/05556 ,  H01L2224/05599 ,  H01L2224/06153 ,  H01L2224/16145 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/48233 ,  H01L2224/48237 ,  H01L2224/48465 ,  H01L2224/49109 ,  H01L2224/49175 ,  H01L2224/49431 ,  H01L2224/85207 ,  H01L2924/00014 ,  H01L2924/01005 ,  H01L2924/01015 ,  H01L2924/10162 ,  H01L2924/14 ,  H01L2924/15153 ,  H01L2924/15165 ,  H01L2924/15787 ,  H01L2924/3025 ,  H01L2224/45099 ,  H01L2924/00 ,  H01L2224/85399

摘要： A semiconductor IC device 100 comprises an active area 102 including a plurality of unit cells 101a and 101b, and a plurality of electrodes 103 disposed in a zigzag fashion along the periphery of the active area 102. Signal I/0 electrodes 103a are disposed on the first row of the zigzag electrode arrangement while the power supply and ground electrodes 103b and 103c are alternately disposed on the second row of the zigzag electrode arrangement. Owing to this constitution, power supply and ground electrode 103b and 103c may exist separately from signal I/0 electrode 103a, so that a sufficient number of power supply and ground electrodes 103b and 103c can be secured even in the case that all of available signal I/0 electrodes 103a are fully used for maximum operation of the circuit portion (active area) 102.

摘要翻译： 半导体IC器件100包括包括多个单位电池101a和101b的有源区域102和沿有源区域102的外围以锯齿形方式设置的多个电极103.信号I / O电极103a设置在 Z字形电极布置的第一行，而电源和接地电极103b和103c交替地设置在Z字形电极装置的第二行上。 由于这种结构，电源和接地电极103b和103c可以与信号I / O电极103a分开存在，使得即使在所有可用信号的情况下也可以确保足够数量的电源和接地电极103b和103c I / O电极103a完全用于电路部分（有效区域）102的最大操作

公开(公告)号：EP0834922A2

公开(公告)日：1998-04-08

申请号：EP97121409.3

申请日：1994-03-23

申请人： Intergraph Corporation

发明人： Boyle, Steve ,  Proebsting, Robert J. ,  Herndon, William H.

IPC分类号： H01L23/66 ,  H01L23/498

CPC分类号： H01L23/49822 ,  H01L23/49838 ,  H01L23/66 ,  H01L24/48 ,  H01L24/49 ,  H01L2223/6638 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/48233 ,  H01L2224/49171 ,  H01L2224/49175 ,  H01L2924/00014 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01015 ,  H01L2924/01019 ,  H01L2924/01023 ,  H01L2924/01072 ,  H01L2924/04953 ,  H01L2924/14 ,  H01L2924/15153 ,  H01L2924/1517 ,  H01L2924/15173 ,  H01L2924/15312 ,  H01L2924/1532 ,  H01L2924/19043 ,  H01L2924/30105 ,  H01L2924/30107 ,  H01L2924/3011 ,  H01L2924/30111 ,  H01L2924/3025 ,  Y10T29/49126 ,  Y10T29/49165 ,  H01L2924/00 ,  H01L2224/45099 ,  H01L2224/05599

摘要： A multi-layered package is disclosed that employs novel shielding techniques to improve high frequency performance of the package. Shield vias (204) are placed near conductive vias (200) to create a two-wire transmission line with controllable characteristic impedance. Controlled transmission line impedance reduces signal reflection due to line impedance variations and ground bounce due to inductive coupling. Opposite polarity shielding technique is introduced in vertical as well as horizontal directions to reduce capacitive coupling of noise between signals and provide immunity against differential power supply noise. Signal layers disposed half way between floating shield planes provided immunity against non-common mode noise coupling. For integrated circuits with varying types of signals ( e.g . CMOS and TTL and ECL type signals), the package creates electrically isolated zones to drastically reduce noise coupling between the circuits with different signal types.

摘要翻译： 公开了采用新型屏蔽技术来改善封装的高频性能的多层封装。 屏蔽过孔（204）被放置在导电过孔（200）附近以形成具有可控特性阻抗的双线传输线。 受控传输线阻抗减少了由于电感耦合引起的线路阻抗变化和接地跳动引起的信号反射。 在垂直和水平方向引入了相反的极性屏蔽技术，以减少信号之间噪声的电容耦合，并提供抗差分电源噪声的能力。 信号层位于浮动屏蔽平面之间的一半处，可以抵抗非共模噪声耦合。 对于具有不同类型信号的集成电路（例如CMOS和TTL和ECL型信号），封装形成电隔离区域，可大幅度降低具有不同信号类型的电路之间的噪声耦合。