公开(公告)号：EP0145557B1

公开(公告)日：1989-07-26

申请号：EP84402304.4

申请日：1984-11-13

Applicant: THOMSON-CSF

Inventor： Lacruche, Bernard ,  Bonhoure, Francis

IPC: H05K3/34 ,  B23K1/08 ,  B23K1/20

CPC classification number: B23K1/20 ,  B23K2201/40 ,  H05K3/305 ,  H05K3/3405 ,  H05K3/3426 ,  H05K3/3442 ,  H05K3/3468 ,  H05K2201/09181 ,  H05K2201/09381 ,  H05K2201/10522 ,  H05K2201/10727 ,  H05K2201/10946 ,  H05K2203/046 ,  H05K2203/1581 ,  Y02P70/613

公开(公告)号：EP0315792A2

公开(公告)日：1989-05-17

申请号：EP88117121.9

申请日：1988-10-14

Applicant: LORAL AEROSPACE CORPORATION

Inventor： Chall, Louis Edmond, Jr.

IPC: H01L23/48 ,  H05K7/20 ,  H01L23/52

CPC classification number: H01L23/52 ,  G01R31/318505 ,  G11C29/006 ,  H01L23/13 ,  H01L23/473 ,  H01L23/5385 ,  H01L2924/0002 ,  H01L2924/15162 ,  H01L2924/3011 ,  H05K1/0286 ,  H05K1/142 ,  H05K3/3442 ,  H05K3/403 ,  H05K7/20545 ,  H05K2201/09181 ,  H05K2201/09418 ,  H05K2201/1053 ,  H05K2201/10727 ,  Y02P70/613 ,  H01L2924/00

Abstract: A novel packaging system for VLSI circuits allows low-cost construction and maintenance of complex high density high-­performance devices with low power requirements. The devices can be individually created by software means from a small selection of standardizable IC chips by disposing a plurality of chips in leadless chip carriers in a mosaic on a substrate, and configuring them by software to selectively communicate with other chips of the mosaic or even to individually change their operating function. The immediate juxtaposition of the chip carries in the mosaic eliminates transmission line data skew, and also allows considerable savings in chip space and power requirements by dispensing with interconnection drivers, receivers and bonding pads. The chip carrier mosaics may be assembled into modules suitable for plug-in connection to an interconnecting backplane to create even larger devices, and individual modules can be dynamically tested in their high-performance mode by configuring one or more modules as test modules and either plugging them into modules to be tested or making them a permanent part of the device's module array.

Abstract translation: 用于VLSI电路的新型封装系统允许低成本构建和维护具有低功耗要求的复杂高密度高性能器件。 通过在基板上的马赛克中的无引线芯片载体中布置多个芯片，并且通过软件来配置它们以选择性地与马赛克的其他芯片进行通信，甚至可以通过软件来从小量的可标准化的IC芯片中分别创建设备 单独改变其操作功能。 芯片中马上并置的马赛克并排消除了传输线数据的偏移，并且通过分配互连驱动器，接收器和接合焊盘，可以大大节省芯片空间和功耗。 芯片载体马赛克可以组装成适合于插入连接到互连背板的模块，以创建更大的设备，并且可以通过将一个或多个模块配置为测试模块和插件来以高性能模式动态测试各个模块 它们被组合成要测试的模块或使其成为设备模块阵列的永久部分。

公开(公告)号：EP0145557A3

公开(公告)日：1985-07-10

申请号：EP84402304

申请日：1984-11-13

Applicant: THOMSON-CSF

Inventor： Lacruche, Bernard ,  Bonhoure, Francis

IPC: H05K03/34 ,  B23K01/08 ,  B23K01/20

CPC classification number: B23K1/20 ,  B23K2201/40 ,  H05K3/305 ,  H05K3/3405 ,  H05K3/3426 ,  H05K3/3442 ,  H05K3/3468 ,  H05K2201/09181 ,  H05K2201/09381 ,  H05K2201/10522 ,  H05K2201/10727 ,  H05K2201/10946 ,  H05K2203/046 ,  H05K2203/1581 ,  Y02P70/613

公开(公告)号：EP0042417A4

公开(公告)日：1984-03-27

申请号：EP81900254

申请日：1980-12-22

Applicant: WESTERN ELECTRIC CO

Inventor： HALL PETER MICHAEL ,  HOWLAND FRANK LESLIE ,  MORABITO JOSEPH MICHAEL ,  RICKABAUGH LAWRENCE JAMES

IPC: H01L23/12 ,  H01L21/58 ,  H01L23/32 ,  H01L23/498 ,  H05K3/34

CPC classification number: H01L24/83 ,  H01L23/49816 ,  H01L24/26 ,  H01L2224/8319 ,  H01L2224/8385 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01012 ,  H01L2924/01015 ,  H01L2924/01023 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01039 ,  H01L2924/01046 ,  H01L2924/0105 ,  H01L2924/01061 ,  H01L2924/01072 ,  H01L2924/01074 ,  H01L2924/01077 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/01084 ,  H01L2924/01327 ,  H01L2924/014 ,  H01L2924/07802 ,  H01L2924/14 ,  H01L2924/15787 ,  H01L2924/19041 ,  H01L2924/19043 ,  H05K3/3436 ,  H05K3/3442 ,  H05K2201/09181 ,  H05K2201/10727 ,  H05K2201/10984 ,  H05K2203/041 ,  Y02P70/613 ,  H01L2924/00

Abstract: A method of fabricating circuit packages which employ macro-components (10) mounted on supporting substrates (20). In order to maintain sufficient clearance between the component and substrate and achieve high reliability bonds, massive solder spheres (16) are applied to contact pads (14) on either the component or substrate. After contact pads of both carrier and substrate are brought into contact with the spheres, the bond is formed by reflowing the solder while maintaining a component to substrate clearance of at least 0.25mm due to surface tension of the solder spheres.

公开(公告)号：EP0023400B1

公开(公告)日：1984-03-21

申请号：EP80302341.5

申请日：1980-07-10

Applicant: FUJITSU LIMITED

Inventor： Honda, Norio ,  Hayashi, Kunihiko

IPC: H01L23/02 ,  H01L23/50

CPC classification number: H01L23/057 ,  H01L23/08 ,  H01L23/13 ,  H01L23/49822 ,  H01L2224/48227 ,  H05K1/0306 ,  H05K1/092 ,  H05K3/3442 ,  H05K3/403 ,  H05K3/4061 ,  H05K3/4611 ,  H05K3/4629 ,  H05K2201/09181 ,  H05K2201/09709 ,  H05K2201/09845

公开(公告)号：EP0098114A2

公开(公告)日：1984-01-11

申请号：EP83303642.9

申请日：1983-06-24

Applicant: FUJITSU LIMITED

Inventor： Tsujimura, Takehisa

IPC: H01L23/48

CPC classification number: H01L23/49805 ,  H01L23/057 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2924/01079 ,  H05K3/3442 ,  H05K2201/09181 ,  H05K2201/09709 ,  H05K2201/10727 ,  Y02P70/613 ,  H01L2924/00014

Abstract: In a leadless chip carrier (LCC) type semiconductor device, a larger number of soldering pads (3, 8) for connection to an external circuit can be formed for a given package size by using different depths of adjacent grooves (611a, 611b, 621a, 621b) formed along the edge face (612, 622) of the package to receive metallization lines (613a, 613b, 623a, 623b). Adjacent soldering pads are therefore located at different depths from the periphery of the package, so that the risk of short circuits caused by solder bridges between adjacent soldering pads is not increased by the increased density.

Abstract translation: 在无引线芯片载体（LCC）型半导体器件中，通过使用相邻的凹槽（611a，611b，621a）的不同深度，可以为给定的封装尺寸形成用于连接到外部电路的更多数量的焊盘（3,8） ，621b）沿着封装的边缘面（612,622）形成以接收金属化线（613a，613b，623a，623b）。 因此，相邻的焊盘位于与封装周边不同的深度处，使得相邻焊盘之间由焊料桥引起的短路的风险不会因密度增加而增加。

公开(公告)号：EP3313156A1

公开(公告)日：2018-04-25

申请号：EP16811249.8

申请日：2016-06-17

Applicant: Nippon Telegraph and Telephone Corporation

Inventor： USUI, Mitsuo ,  KIKUCHI, Kiyofumi ,  TSUZUKI, Ken ,  FUKUDA, Hiroshi ,  ASAKAWA, Shuichiro ,  KAMEI, Shin ,  SOMA, Shunichi ,  SAIDA, Takashi

IPC: H05K1/14 ,  H05K1/11 ,  H05K3/36

CPC classification number: H05K3/363 ,  H05K1/0269 ,  H05K1/11 ,  H05K1/111 ,  H05K1/117 ,  H05K1/14 ,  H05K1/147 ,  H05K1/189 ,  H05K3/3463 ,  H05K3/36 ,  H05K3/403 ,  H05K2201/09181 ,  H05K2201/09409 ,  H05K2201/10121

Abstract: In a conventional soldering method, an FPC-side electrode pad and a package-side electrode pad are closely joined together with a solder layer, and the soldered state after a joining process has not been easily confirmed visually. Since a conduction inspection on wirings by measuring resistance values, for example, for an electric path including a joint portion needs to be made, quite a long time has been required for the inspection. The present invention provides a solder joint structure including a side face electrode which is formed on each of the side faces of the end parts of an FPC board and a package or PCB board that are to be soldered, extending vertically relative to the faces constituting each of electrode pads on the boards , and which introduces solder. On the side face electrodes of the board end parts, a part of solder that is formed continuously from the solder joint portion is visible and the state of the solder joint between the electrode pads on the two boards can be confirmed. The efficiency of solder joint tests can be improved by providing an electrode pad configuration which allows to form solder joint portions that are sufficiently visible from the side faces of the boards.

Abstract translation: 在传统的焊接方法中，FPC侧电极焊盘和封装侧电极焊盘通过焊料层紧密接合在一起，并且接合工艺之后的焊接状态不容易在视觉上确认。 由于需要通过测量电阻值来进行布线的导通检查，例如对于包括接头部分的电气路径，所以检查需要相当长的时间。 本发明提供了一种钎焊接合结构，其包括形成在FPC板的端部的每个侧面上的侧面电极和待焊接的封装或PCB板，所述侧面电极相对于构成每个 电路板上的电极焊盘，并引入焊料。 在电路板端部的侧面电极上，从焊接部分连续形成的焊料的一部分是可见的，并且可以确认两个电路板上的电极焊盘之间的焊接状态。 通过提供允许形成从板的侧面足够可见的焊点部分的电极焊盘配置，可以提高焊点测试的效率。

公开(公告)号：EP2899802B1

公开(公告)日：2017-11-01

申请号：EP15150480.0

申请日：2015-01-08

Applicant: Honeywell International Inc.

Inventor： Wang, Nan ,  Wang, Chao ,  Nyhus, Orville

IPC: H01P3/08 ,  H01P5/02 ,  H01P11/00 ,  H01Q1/50 ,  H01Q21/00 ,  H01P1/30 ,  H02H1/04 ,  H01P1/04 ,  H05K1/14 ,  H05K3/36 ,  H01Q21/08

CPC classification number: H01P5/028 ,  H01P1/047 ,  H01P1/30 ,  H01P3/085 ,  H01Q1/50 ,  H01Q21/0075 ,  H01Q21/08 ,  H02H1/04 ,  H05K1/142 ,  H05K3/36 ,  H05K2201/09181 ,  H05K2201/09845 ,  Y10T29/49126

Abstract: An anti-lightning-combined-stripline-circuit system is provided. The anti-lightning-combined-stripline-circuit system includes a stripline board including circuitry, and a metal ground bar attached to the stripline board. The metal ground bar has a geometry configured to function as a ground for the circuitry and simultaneously function as a lightning ground for a linear array of elements driven by the circuitry.

公开(公告)号：EP3236536A1

公开(公告)日：2017-10-25

申请号：EP16863208.1

申请日：2016-10-10

Applicant: BOE Technology Group Co., Ltd.

Inventor： LU, Yongjie

IPC: H01R13/28

CPC classification number: H01R13/629 ,  H01R12/777 ,  H01R13/20 ,  H01R13/28 ,  H05K1/118 ,  H05K3/365 ,  H05K2201/09181 ,  H05K2201/09709 ,  H05K2201/2072

Abstract: The embodiments of the present disclosure relate to a zipper type electrical connector comprising: a first chain and a second chain; a plurality of engaging elements provided on the first and second chains respectively; and a slider slidably connected to the first and second chains, such that the engaging elements on the first and second chains are switched between an engaged state and a disengaged state; wherein, in the engaged state, the engaging elements on the first chain and those on the second chain are arranged closely and staggered with respect to each other, and at least one of the engaging elements on one of the first and second chains and at least one of the engaging elements on the other of the first and second chains are connected to each other to achieve an electrical connection; in the disengaged state, the engaging elements on the first chain is disengaged from those on the second chain, and the engaging elements on the first and second chains are electrically insulated from each other.

Abstract translation: 本实用新型涉及一种拉链式电连接器，包括：第一链条和第二链条; 多个接合元件，分别设置在第一和第二链条上; 以及可滑动地连接到所述第一和第二链条的滑块，使得所述第一和第二链条上的所述接合元件在接合状态和脱离状态之间切换; 其中，在所述接合状态下，所述第一链条上的所述接合元件和所述第二链条上的所述接合元件彼此紧密地错开布置，并且所述第一链条和所述第二链条中的一个上的所述接合元件中的至少一个和至少 第一链条和第二链条中的另一个上的接合元件中的一个彼此连接以实现电连接; 在脱离状态下，第一链条上的接合元件与第二链条上的接合元件脱离，并且第一链条和第二链条上的接合元件彼此电绝缘。

公开(公告)号：EP2945146A1

公开(公告)日：2015-11-18

申请号：EP14738176.8

申请日：2014-01-08

Applicant: GWS Technology Co., Ltd.

Inventor： LIN, Yi

IPC: G09F9/33

CPC classification number: F21K9/20 ,  F21K9/90 ,  F21V23/005 ,  F21Y2115/10 ,  G09F9/33 ,  H05K1/18 ,  H05K3/328 ,  H05K3/3405 ,  H05K3/403 ,  H05K2201/09163 ,  H05K2201/09181 ,  H05K2201/10106 ,  H05K2201/10446 ,  Y10T29/4913

Abstract: An LED screen display unit and production method therefor. The LED screen display unit comprises a circuit board (1), a driving IC (2) and LEDs (3); a first face of said circuit board (1) is provided with a contact pad matrix (41); the driving IC (2) is arranged on the circuit board (1) and is in electrical connection with contact pads (4) of said contact pad matrix (41); the pins (31) of the LEDs (3) are soldered to contact pads (4) of the contact pad matrix (41). The present display unit can ensure a higher permeability rate for LED display screens produced having high pixel density.

Abstract translation: 一种LED显示屏及其制作方法。 LED屏显示单元包括电路板（1），驱动IC（2）和LED（3）; 所述电路板（1）的第一面设置有接触垫矩阵（41）; 驱动IC（2）布置在电路板（1）上并与所述接触垫矩阵（41）的接触焊盘（4）电连接; LED（3）的引脚（31）焊接到接触垫矩阵（41）的接触焊盘（4）。 本显示单元可以确保具有高像素密度的LED显示屏的更高的透射率。