公开(公告)号：EP1737037A3

公开(公告)日：2008-08-20

申请号：EP06012984.8

申请日：2006-06-23

申请人： Megica Corporation

发明人： Lin, Mou-Shiung ,  Chou, Chien-Kang ,  Chen, Ke-Hung

IPC分类号： H01L23/485 ,  H01L23/31 ,  H01L21/60

CPC分类号： H01L23/5227 ,  H01L21/2885 ,  H01L21/563 ,  H01L21/76801 ,  H01L21/76885 ,  H01L23/3114 ,  H01L23/5223 ,  H01L24/03 ,  H01L24/05 ,  H01L24/11 ,  H01L24/12 ,  H01L24/16 ,  H01L24/45 ,  H01L24/48 ,  H01L24/83 ,  H01L2224/0347 ,  H01L2224/0401 ,  H01L2224/04042 ,  H01L2224/04073 ,  H01L2224/05173 ,  H01L2224/05176 ,  H01L2224/05183 ,  H01L2224/05548 ,  H01L2224/05571 ,  H01L2224/05572 ,  H01L2224/05639 ,  H01L2224/05644 ,  H01L2224/05647 ,  H01L2224/05664 ,  H01L2224/05669 ,  H01L2224/1147 ,  H01L2224/13022 ,  H01L2224/13099 ,  H01L2224/131 ,  H01L2224/16 ,  H01L2224/45139 ,  H01L2224/45144 ,  H01L2224/45147 ,  H01L2224/45155 ,  H01L2224/45164 ,  H01L2224/45169 ,  H01L2224/45173 ,  H01L2224/45176 ,  H01L2224/45183 ,  H01L2224/48091 ,  H01L2224/48463 ,  H01L2224/48639 ,  H01L2224/48644 ,  H01L2224/48647 ,  H01L2224/48664 ,  H01L2224/48669 ,  H01L2224/48839 ,  H01L2224/48844 ,  H01L2224/48847 ,  H01L2224/48864 ,  H01L2224/83101 ,  H01L2224/83192 ,  H01L2924/00011 ,  H01L2924/00014 ,  H01L2924/0002 ,  H01L2924/014 ,  H01L2924/04941 ,  H01L2924/04953 ,  H01L2924/05042 ,  H01L2924/09701 ,  H01L2924/10329 ,  H01L2924/12044 ,  H01L2924/1305 ,  H01L2924/13091 ,  H01L2924/14 ,  H01L2924/15787 ,  H01L2924/15788 ,  H01L2924/19041 ,  H01L2924/19042 ,  H01L2924/19043 ,  H01L2924/30105 ,  H01L2924/30107 ,  H01L2924/3011 ,  H01L2924/351 ,  H01L2924/00 ,  H01L2224/48869 ,  H01L2224/83851 ,  H01L2224/05552 ,  H01L2224/05599

摘要： A circuit structure includes a semiconductor substrate, first and second metallic posts over the semiconductor substrate, an insulating layer over the semiconductor substrate and covering the first and second metallic posts, first and second bumps over the first and second metallic posts or over the insulating layer. The first and second metallic posts have a height of between 20 and 300 microns, with the ratio of the maximum horizontal dimension thereof to the height thereof being less than 4. The distance between the center of the first bump and the center of the second bump is between 10 and 250 microns.

公开(公告)号：EP1801849A3

公开(公告)日：2008-07-02

申请号：EP06026547.7

申请日：2006-12-21

申请人： SANYO ELECTRIC CO. LTD

发明人： Noma, Takashi

IPC分类号： H01L31/0232

CPC分类号： H01L27/14618 ,  H01L23/3164 ,  H01L24/05 ,  H01L24/11 ,  H01L24/13 ,  H01L27/14687 ,  H01L2224/0401 ,  H01L2224/04042 ,  H01L2224/05124 ,  H01L2224/05147 ,  H01L2224/05571 ,  H01L2224/05573 ,  H01L2224/05644 ,  H01L2224/05655 ,  H01L2224/06154 ,  H01L2224/10125 ,  H01L2224/1131 ,  H01L2224/1132 ,  H01L2224/11462 ,  H01L2224/1148 ,  H01L2224/11849 ,  H01L2224/13022 ,  H01L2224/131 ,  H01L2224/13144 ,  H01L2224/14135 ,  H01L2224/14154 ,  H01L2224/16225 ,  H01L2224/16227 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/81141 ,  H01L2924/00013 ,  H01L2924/0002 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01015 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01047 ,  H01L2924/01057 ,  H01L2924/01072 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/12042 ,  H01L2924/15788 ,  H04N5/2257 ,  H01L2924/00014 ,  H01L2224/13099 ,  H01L2224/13599 ,  H01L2224/05599 ,  H01L2224/05099 ,  H01L2224/29099 ,  H01L2224/29599 ,  H01L2224/05552 ,  H01L2924/00

摘要： The invention provides a package type semiconductor device and a method of manufacturing the same where reliability and yield are enhanced without making a manufacturing process complex. A resin layer (6) and a supporting body (7) are formed on a front surface of a semiconductor substrate (2) formed with a pad electrode (4). Then, the resin layer (6) and the supporting body (7) are removed by etching so as to expose the pad electrode (4). By this etching, the supporting body (7) in two conductive terminal formation regions facing each other over a dicing line (x) and the supporting body in a region connecting with these regions therebetween are simultaneously removed to form an opening (10). Then, a metal layer is formed on the pad electrode (4) exposed in the opening, and a conductive terminal is further formed thereon. Lastly, dicing is performed along the dicing line to separate the semiconductor substrate in individual semiconductor dies.

公开(公告)号：EP1922755A2

公开(公告)日：2008-05-21

申请号：EP06789625.8

申请日：2006-08-09

申请人： Texas Instruments Incorporated

发明人： ANO, Kazuaki

IPC分类号： H01L23/48 ,  H01L23/52 ,  H01L29/40

CPC分类号： H01L24/48 ,  H01L23/498 ,  H01L23/49816 ,  H01L24/45 ,  H01L24/73 ,  H01L24/85 ,  H01L2224/0401 ,  H01L2224/05548 ,  H01L2224/05567 ,  H01L2224/13022 ,  H01L2224/32225 ,  H01L2224/45144 ,  H01L2224/48227 ,  H01L2224/48465 ,  H01L2224/48599 ,  H01L2224/48644 ,  H01L2224/48799 ,  H01L2224/48844 ,  H01L2224/73265 ,  H01L2224/85444 ,  H01L2924/00011 ,  H01L2924/0002 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01015 ,  H01L2924/01028 ,  H01L2924/01029 ,  H01L2924/0103 ,  H01L2924/01033 ,  H01L2924/01046 ,  H01L2924/01047 ,  H01L2924/01049 ,  H01L2924/0105 ,  H01L2924/01051 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/01083 ,  H01L2924/01327 ,  H01L2924/014 ,  H01L2924/14 ,  H01L2924/15311 ,  H01L2924/181 ,  H01L2924/3025 ,  H05K3/244 ,  H05K3/3463 ,  H01L2924/00014 ,  H01L2924/00 ,  H01L2924/00012 ,  H01L2224/05552

摘要： A device with a solder joint made of a copper contact pad ( 210 ) of certain area ( 202 ) and an alloy layer ( 301 ) metallurgically attached to the copper pad across the pad area. The alloy layer contains copper/tin alloys, which include Cu 6 Sn 5 intermetallic compound, and nickel/copper/tin alloys, which include (Ni,Cu) 6 Sn 5 intermetallic compound. A solder element ( 308 ) including tin is metallurgically attached to the alloy layer across the pad area. No fraction of the original thin nickel layer is left after the reflow process. Copper/tin alloys help to improve the drop test performance, nickel/copper/tin alloys help to improve the life test performance.

摘要翻译： 一种具有由特定区域（202）的铜接触焊盘（210）和合金层（301）制成的焊接接头的器件，其在冶金上附着到穿过焊盘区域的铜焊盘。 该合金层包含铜/锡合金，其包括Cu 6 Sn 5+金属间化合物，和镍/铜/锡合金，其包括（Ni，Cu） 6 5 5 金属间化合物。 包括锡的焊料元件（308）通过焊盘区域冶金地附接到合金层。 在回流处理之后，不存在原始薄镍层的一部分。 铜/锡合金有助于提高跌落测试性能，镍/铜/锡合金有助于提高寿命测试性能。

公开(公告)号：EP1798769A2

公开(公告)日：2007-06-20

申请号：EP06026088.2

申请日：2006-12-15

申请人： Sanyo Electric Co., Ltd. ,  Sanyo Semiconductor Co., Ltd.

发明人： Okada, Kazuo ,  Kitagawa, Katsuhiko ,  Noma, Takashi ,  Otsuka, Shigeki ,  Yamada, Hiroshi ,  Ishibe, Shinzo ,  Morita, Yuichi ,  Okubo, Noboru ,  Shinogi, Hiroyuki ,  Okigawa, Mitsuru

IPC分类号： H01L27/146 ,  H01L31/0203 ,  H01L31/0232

CPC分类号： H01L27/14618 ,  H01L23/481 ,  H01L27/14625 ,  H01L31/0203 ,  H01L31/02327 ,  H01L2224/02371 ,  H01L2224/02372 ,  H01L2224/0401 ,  H01L2224/05 ,  H01L2224/05548 ,  H01L2224/13022 ,  H01L2224/13024 ,  H01L2224/131 ,  H01L2924/014

摘要： The invention provides a semiconductor device that solves a problem of reflection of a pattern of a wiring (9) formed on a back surface of a semiconductor substrate (2) on an output image. A reflection layer (8) is formed between a light receiving element (1) and a wiring layer (9), that reflects an infrared ray toward a light receiving element (1) the without transmitting it to the wiring layer (9), the infrared ray entering from a light transparent substrate (6) toward the wiring layer (9) through a semiconductor substrate (2). The reflection layer (8) is formed at least in a region under the light receiving element (1) uniformly or only under the light receiving element (1). Alternatively, an anti-reflection layer having a function of absorbing the entering infrared ray to prevent transmission thereof may be formed instead of the reflection layer.

摘要翻译： 本发明提供了一种半导体器件，其解决了在输出图像上形成在半导体衬底（2）的背表面上的布线（9）的图案的反射问题。 在光接收元件（1）和布线层（9）之间形成反射层（8），该反射层（8）将红外线朝向光接收元件（1）反射而不将其传输到布线层（9）， （6）通过半导体衬底（2）向布线层（9）入射的红外线。 至少在光接收元件（1）下方的区域中均匀地或仅在光接收元件（1）下方形成反射层（8）。 或者，可以形成具有吸收进入的红外线以防止其透射的功能的抗反射层来代替反射层。

公开(公告)号：EP1748478A3

公开(公告)日：2007-05-09

申请号：EP06117534.5

申请日：2006-07-20

申请人： Palo Alto Research Institute Incorporated

发明人： Fork, David K ,  Hantschel, Thomas ,  Chabinyc, Michael L

IPC分类号： H01L21/48

CPC分类号： H05K3/321 ,  B82Y30/00 ,  H01L21/4853 ,  H01L21/6835 ,  H01L24/03 ,  H01L24/05 ,  H01L24/11 ,  H01L24/12 ,  H01L24/29 ,  H01L24/83 ,  H01L24/90 ,  H01L2224/03912 ,  H01L2224/0401 ,  H01L2224/05624 ,  H01L2224/05644 ,  H01L2224/05647 ,  H01L2224/11332 ,  H01L2224/11334 ,  H01L2224/11442 ,  H01L2224/1147 ,  H01L2224/1148 ,  H01L2224/1182 ,  H01L2224/11901 ,  H01L2224/13022 ,  H01L2224/13078 ,  H01L2224/13144 ,  H01L2224/1357 ,  H01L2224/136 ,  H01L2224/29101 ,  H01L2224/29399 ,  H01L2224/81801 ,  H01L2224/838 ,  H01L2924/00013 ,  H01L2924/01004 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01014 ,  H01L2924/01019 ,  H01L2924/01027 ,  H01L2924/01029 ,  H01L2924/0103 ,  H01L2924/01033 ,  H01L2924/01046 ,  H01L2924/01047 ,  H01L2924/01049 ,  H01L2924/0105 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/014 ,  H01L2924/14 ,  H01L2924/15788 ,  H05K3/102 ,  H05K2203/122 ,  H01L2924/00014 ,  H01L2224/13099 ,  H01L2924/00

摘要： A method of forming a self-assembled interconnect structure is described. In the method, a contact pad (104) surface and particles (304) in a solution are brought together. The particles are selected such that they the particles adhere to the contact pad surface. Formation of a contact is completed by pressing an opposite contact into the particles such that an electrical connection is formed via the particles between the opposite contact pad and the substrate surface contact pad. The described self-assembled interconnect structure is particularly useful in display device fabrication.

摘要翻译： 描述了形成自组装互连结构的方法。 在该方法中，将溶液中的接触垫（104）表面和颗粒（304）放在一起。 选择颗粒使得它们的颗粒粘附到接触垫表面。 通过将相对的接触点压入粒子中来完成接触的形成，使得通过相对的接触焊盘和衬底表面接触焊盘之间的粒子形成电连接。 所描述的自组装互连结构在显示装置制造中特别有用。

公开(公告)号：EP1482553A3

公开(公告)日：2007-03-28

申请号：EP04012460.4

申请日：2004-05-26

申请人： SANYO ELECTRIC CO., LTD.

发明人： Takao, Yukihiro

IPC分类号： H01L23/498

CPC分类号： H01L24/12 ,  H01L21/76898 ,  H01L23/3114 ,  H01L23/481 ,  H01L24/11 ,  H01L2224/0231 ,  H01L2224/0401 ,  H01L2224/05124 ,  H01L2224/05147 ,  H01L2224/05155 ,  H01L2224/05166 ,  H01L2224/05171 ,  H01L2224/05181 ,  H01L2224/05548 ,  H01L2224/05644 ,  H01L2224/1148 ,  H01L2224/13022 ,  H01L2224/13099 ,  H01L2224/16 ,  H01L2924/01013 ,  H01L2924/01019 ,  H01L2924/01022 ,  H01L2924/01024 ,  H01L2924/01029 ,  H01L2924/01032 ,  H01L2924/01033 ,  H01L2924/01073 ,  H01L2924/01074 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/04941 ,  H01L2924/04953 ,  H01L2924/10253 ,  H01L2924/10329 ,  H01L2924/12042 ,  H01L2924/14 ,  H01L2924/00 ,  H01L2924/00014 ,  H01L2924/013

摘要： A BGA type semiconductor device having high reliability is offered. A pad electrode (53) is formed on a surface of a semiconductor substrate (51) and a glass substrate (56) is bonded to the surface of the semiconductor substrate. A via hole (VH) is formed from a back surface of the semiconductor substrate (51) to reach a surface of the pad electrode (53). An insulation film is formed on an entire back surface of the semiconductor substrate (51) including an inside of the via hole (VH). A cushioning pad (60) is formed on the insulation film. The insulation film is removed from a bottom portion of the via hole (VH) by etching. A wiring (63) connected with the pad electrode (53) is formed to extend from the via hole (VH) onto the cushioning pad (60). A conductive terminal (66) is formed on the wirinq (63). Then the semiconductor substrate (51) is separated into a plurality of semiconductor dice.

摘要翻译： 提供具有高可靠性的BGA型半导体器件。 在半导体衬底（51）的表面上形成焊盘电极（53），并且将玻璃衬底（56）接合到半导体衬底的表面。 从半导体基板（51）的背面形成通路孔（VH），到达焊盘电极（53）的表面。 绝缘膜形成在包括通孔（VH）的内部的半导体衬底（51）的整个背表面上。 缓冲垫（60）形成在绝缘膜上。 通过蚀刻从通孔（VH）的底部去除绝缘膜。 与焊盘电极（53）连接的布线（63）形成为从通孔（VH）延伸到缓冲垫（60）上。 导电端子（66）形成在导线（63）上。 然后将半导体衬底（51）分成多个半导体芯片。

公开(公告)号：EP1748478A2

公开(公告)日：2007-01-31

申请号：EP06117534.5

申请日：2006-07-20

申请人： Palo Alto Research Institute Incorporated

发明人： Fork, David K ,  Hantschel, Thomas ,  Chabinyc, Michael L

IPC分类号： H01L21/48

CPC分类号： H05K3/321 ,  B82Y30/00 ,  H01L21/4853 ,  H01L21/6835 ,  H01L24/03 ,  H01L24/05 ,  H01L24/11 ,  H01L24/12 ,  H01L24/29 ,  H01L24/83 ,  H01L24/90 ,  H01L2224/03912 ,  H01L2224/0401 ,  H01L2224/05624 ,  H01L2224/05644 ,  H01L2224/05647 ,  H01L2224/11332 ,  H01L2224/11334 ,  H01L2224/11442 ,  H01L2224/1147 ,  H01L2224/1148 ,  H01L2224/1182 ,  H01L2224/11901 ,  H01L2224/13022 ,  H01L2224/13078 ,  H01L2224/13144 ,  H01L2224/1357 ,  H01L2224/136 ,  H01L2224/29101 ,  H01L2224/29399 ,  H01L2224/81801 ,  H01L2224/838 ,  H01L2924/00013 ,  H01L2924/01004 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01014 ,  H01L2924/01019 ,  H01L2924/01027 ,  H01L2924/01029 ,  H01L2924/0103 ,  H01L2924/01033 ,  H01L2924/01046 ,  H01L2924/01047 ,  H01L2924/01049 ,  H01L2924/0105 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/014 ,  H01L2924/14 ,  H01L2924/15788 ,  H05K3/102 ,  H05K2203/122 ,  H01L2924/00014 ,  H01L2224/13099 ,  H01L2924/00

摘要： A method of forming a self-assembled interconnect structure is described. In the method, a contact pad (104) surface and particles (304) in a solution are brought together. The particles are selected such that they the particles adhere to the contact pad surface. Formation of a contact is completed by pressing an opposite contact into the particles such that an electrical connection is formed via the particles between the opposite contact pad and the substrate surface contact pad. The described self-assembled interconnect structure is particularly useful in display device fabrication.

摘要翻译： 描述形成自组装互连结构的方法。 在该方法中，将溶液中的接触垫（104）表面和颗粒（304）聚集在一起。 颗粒被选择成使得颗粒粘附到接触垫表面。 通过将相对的触点压入颗粒中，使得通过相对的接触垫和基板表面接触垫之间的颗粒形成电连接来完成接触的形成。 所描述的自组装互连结构在显示器件制造中特别有用。

公开(公告)号：EP1737036A2

公开(公告)日：2006-12-27

申请号：EP06012324.7

申请日：2006-06-14

申请人： Sanyo Electric Co., Ltd

发明人： Morita, Yuichi ,  Ishibe, Shinzo ,  Noma, Takashi ,  Otsuka, Hisao ,  Takao, Yukihiro ,  Kanamori, Hiroshi

IPC分类号： H01L23/485 ,  H01L21/60

CPC分类号： H01L24/13 ,  H01L23/3192 ,  H01L24/11 ,  H01L2224/05001 ,  H01L2224/05022 ,  H01L2224/05124 ,  H01L2224/05147 ,  H01L2224/05155 ,  H01L2224/05568 ,  H01L2224/05644 ,  H01L2224/1191 ,  H01L2224/13022 ,  H01L2224/13099 ,  H01L2224/131 ,  H01L2224/13144 ,  H01L2924/0001 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/13091 ,  H01L2924/00014 ,  H01L2924/00

摘要： The invention provides a CSP type semiconductor device with high reliability.
The semiconductor device includes a pad electrode (4) formed on a semiconductor substrate (1) with insulation films (2, 3) interposed therebetween, a plating layer (7) formed on the pad electrode (4), a conductive terminal (9) formed on the plating layer and electrically connected with the pad electrode (4), and a first passivation film (5) covering the insulation films (2, 3) and a side end portion of the pad electrode (4), in which an exposed portion of the pad electrode (4) that causes corrosion is covered by forming a second passivation film (10) so as to cover the first passivation film (5), the plating layer (7), and a portion of a sidewall of the conductive terminal (9).

摘要翻译： 本发明提供了一种具有高可靠性的CSP型半导体器件。 半导体器件包括形成在半导体衬底（1）上的绝缘膜（2,3）的焊盘电极（4），形成在焊盘电极（4）上的镀层（7），导电端子（9） 形成在所述镀层上并与所述焊盘电极（4）电连接;以及覆盖所述绝缘膜（2,3）的第一钝化膜（5）和所述焊盘电极（4）的侧端部， 通过形成第二钝化膜（10）覆盖引起腐蚀的焊盘电极（4）的一部分，以覆盖第一钝化膜（5），镀层（7）和导电的侧壁的一部分 终端（9）。

公开(公告)号：EP1653510A2

公开(公告)日：2006-05-03

申请号：EP05023591.0

申请日：2005-10-28

申请人： SANYO ELECTRIC CO., LTD. ,  Kanto Sanyo Semiconductors Co., Ltd.

发明人： Kameyama, Kojiro ,  Suzuki, Akira ,  Umemoto, Mitsuo

IPC分类号： H01L23/485 ,  H01L23/48 ,  H01L21/768

CPC分类号： H01L21/76898 ,  H01L23/3114 ,  H01L23/481 ,  H01L24/02 ,  H01L24/10 ,  H01L24/12 ,  H01L2224/0231 ,  H01L2224/0392 ,  H01L2224/0401 ,  H01L2224/13022 ,  H01L2224/16 ,  H01L2924/01078 ,  H01L2924/04941

摘要： A first pad electrode layer (12) is disposed on a surface of a semiconductor substrate (10) with a first insulating film (11) between them. Then, a second insulating film (13) with a first via hole partially exposing a first pad electrode layer (12) is formed over the first pad electrode layer (12). A plug (14) is formed in the first via hole in the next process. The second pad electrode layer (15) connected to the plug (14) is disposed on the second insulating film (13). Next, a second via hole (102) reaching to the first pad electrode layer (13) from the backside of the semiconductor substrate (10) is formed. A penetrating electrode (20) and a second wiring layer (21) connected to the first pad electrode layer (13) at the bottom part of the second via hole (102) are disposed. Furthermore, a protecting layer (22) and a conductive terminal (23) are formed. Finally, the semiconductor substrate (10) is diced into the semiconductor chips.

摘要翻译： 第一焊盘电极层（12）设置在半导体衬底（10）的表面上，其间具有第一绝缘膜（11）。 然后，在第一焊盘电极层（12）上形成具有部分暴露第一焊盘电极层（12）的第一通孔的第二绝缘膜（13）。 在下一个工艺中，在第一通孔中形成插塞（14）。 连接到插塞（14）的第二焊盘电极层（15）设置在第二绝缘膜（13）上。 接着，形成从半导体基板（10）的背面到达第一焊盘电极层（13）的第二通孔（102）。 在第二通孔（102）的底部设置有穿透电极（20）和连接到第一焊盘电极层（13）的第二布线层（21）。 此外，形成保护层（22）和导电端子（23）。 最后，将半导体衬底（10）切割成半导体芯片。

公开(公告)号：EP1030359A3

公开(公告)日：2002-08-21

申请号：EP99125339.4

申请日：1999-12-20

申请人： Micronas GmbH

发明人： Igel, Günter Dipl.-Ing. ,  Gahle, Jürgen Dr. Ing. ,  Lehmann, Mirko Dipl. Phys.

IPC分类号： H01L21/60 ,  H01L23/485

CPC分类号： H01L24/12 ,  H01L23/3192 ,  H01L24/11 ,  H01L2224/13018 ,  H01L2224/13022 ,  H01L2224/13099 ,  H01L2224/13144 ,  H01L2224/13147 ,  H01L2924/01004 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01022 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01046 ,  H01L2924/01047 ,  H01L2924/01049 ,  H01L2924/01074 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/14 ,  H01L2924/19043 ,  H01L2924/351 ,  H01L2924/00

摘要： Bei einem Verfahren zum Herstellen einer einen Bump für eine Flip-Chip- oder dergleichen Verbindung aufweisenden Schichtanordnung (1) werden mehrere Schichten (2, 3, 4, 5, 6, 7, 11) aus Festkörpermaterial zu einem Schichtstapel (8) geschichtet. In den Schichtstapel (8) wird quer zu den Schichtungsebenen der Schichten (2, 3, 4, 5, 6, 7, 11) eine sich über mehrere der Schichten (2, 3, 4, 5, 6, 7, 11) erstreckende Ausnehmung (10) eingebracht. In die Ausnehmung (10) wird ein Bump-Material (14) eingebracht. An der seitlichen Begrenzungswand der Ausnehmung (10) durch Abtragen von Schichtmaterial unterschiedlicher Schichten (2, 3, 4, 5, 6, 7, 11) des Schichtstapels (8) eine Profilierung erzeugt wird, die ausgehend von der Oberfläche (9) des Schichtstapels (8) zum Inneren der Ausnehmung (10) hin schichtweise wenigstens zwei Rücksprünge (12) und zumindest einen dazwischen befindlichen Vorsprung (13) aufweist. Nach dem Fertigstellen der Profilierung wird ein Bump-Material (14) in die Ausnehmung (10) eingebracht, das die Rücksprünge (12) hintergreift.