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    STACKED VIAS FOR VERTICAL INTEGRATION
    72.
    发明公开
    STACKED VIAS FOR VERTICAL INTEGRATION 审中-公开
    STACKED经文纵向整合

    公开(公告)号：EP2768767A1

    公开(公告)日：2014-08-27

    申请号：EP12781228.7

    申请日：2012-10-17

    申请人： Qualcomm Mems Technologies, Inc.

    发明人： PAN, Yaoling ,  ZHOU, Lixia

    IPC分类号： B81B7/00 ,  B81C1/00

    CPC分类号： B81B7/0006 ,  B81C1/00246

    摘要： This disclosure provides systems, methods and apparatus for a via structure. In one aspect, an apparatus includes a substrate and a first electromechanical systems device on a surface of the substrate. The first electromechanical systems device includes a first metal layer and a second metal layer. A first via structure can be included on the surface of the substrate. The first via structure includes the first metal layer, the second metal layer, and a third metal layer. The first metal layer of the first electromechanical systems device may be the same metal layer as the first metal layer of the first via structure.

    Method for forming MEMS devices having low contact resistance and devices obtained thereof
    75.
    发明公开
    Method for forming MEMS devices having low contact resistance and devices obtained thereof 审中-公开
    一种用于与低接触电阻的MEMS器件和由此获得的器件的形成过程

    公开(公告)号：EP2277823A3

    公开(公告)日：2013-09-11

    申请号：EP10075263.3

    申请日：2010-06-18

    申请人： IMEC ,  Katholieke Universiteit Leuven, K.U. Leuven R&D

    发明人： Jain, Ajay ,  Severi, Simone ,  Claes, Gert ,  Heck, John

    IPC分类号： B81C1/00

    CPC分类号： B81C1/00246 ,  B81B2203/0118 ,  B81B2207/015 ,  B81B2207/07 ,  B81C2203/0714 ,  B81C2203/0735

    摘要： The present disclosure proposes a method for manufacturing in a MEMS device a low-resistance contact between a silicon-germanium layer and a layer contacted by this silicon-germanium layer, such as a CMOS metal layer or another silicon-germanium layer, through an opening in a dielectric layer stack separating both layers. An interlayer is formed in this opening, thereby covering at least the sidewalls of the opening on the exposed surface of the another layer at the bottom of this opening. This interlayer may comprise a TiN layer in contact with the silicon-germanium layer. This interlayer can further comprise a Ti layer in between the TiN layer and the layer to be contacted. In another embodiment this interlayer comprises a TaN layer in contact with the silicon-germanium layer. This interlayer can then further comprise a Ta layer in between the TaN layer and the layer to be contacted.