公开(公告)号：EP0107387A2

公开(公告)日：1984-05-02

申请号：EP83305837.3

申请日：1983-09-28

申请人： FUJITSU LIMITED

发明人： Takemae, Yoshihiro ,  Nakano, Tomio ,  Sato, Kimiaki

IPC分类号： G11C11/24

CPC分类号： G11C11/4096 ,  G11C11/406 ,  G11C11/4087

摘要： A dynamic memory having single element storage cells (20). One side of a plurality of gates (24,32) are connected to both ends of column lines (CLO to CL511) of the storage cell array. A plurality of sense amplifiers (SAO to SA511) are disposed along both ends of the column lines and connected to the other side of the gate circuits. In accordance with switching of the gate circuits, a part of the sense amplifiers are communicated with a part of the column lines so as to execute the refresh operation and read out or write in operation of the communicate storage cells. Also the remaining sense amplifiers are communicated with the remaining column lines to execute only the refresh operation of the storage cells coupled to the remaining column lines.

公开(公告)号：EP0100432A2

公开(公告)日：1984-02-15

申请号：EP83106291.4

申请日：1983-06-28

申请人： SIEMENS AKTIENGESELLSCHAFT

发明人： Frieling, Focko, Dipl.-Ing. ,  Michael, Ewald, Dipl.-Phys.

IPC分类号： G11C11/24 ,  G11C8/00

CPC分类号： H03K19/01735 ,  G11C8/06 ,  G11C11/4082 ,  G11C11/4087

摘要： Die Erfindung hat die Aufgabe, einen - insbesondere als Adreßpuffer für schnelle dynamische RAM-Speicher geeigneten - Signal-Pegelwandler anzugeben, der mit einem Minimum an Verzögerungszeit arbeitet und in MOS-Technik mit Feldeffekttransistoren vom selben Typ ausgeführt ist. Die erfindungsgemäße Schaltung für einen Signal-Pegelwandler ist so ausgelegt, daß sie mittels eines Differenzverstärkers ein die Abweichung des Wirkungspegels des den Wandler steuernden externen Digitalsignals vom Wirkungspegel der intern in der über den Signal-Pegelwandler zu beaufschlagenden integrierten Halbleiterschaltung laufenden Digitalsignale angebendes Differenzsignal bildet und dieses zur Steuerung eines dynamisch betriebenen und mit zwei Signalausgängen versehenen Ausgangsschaltungsteils verwendet. Der Ausgangsschaltungsteil des Signal-Pegelwandlers besteht aus zwei am Bezugspotential liegenden RS-Flip-Flops sowie aus zwei MOS-Feldeffekttransistoren, deren Sourceanschlüsse je einen der beiden Signalausgänge bilden und mit dem nichtinvertierenden Ausgang je eines der beiden RS-Flip-Flops verbunden sind. Die Drainanschlüsse der beiden MOS-Feldeffekttransistoren werden gemeinsam durch ein Hilfssignal getaktet, während die Beaufschlagung der Ausgangsschaltung von seiten des Differenzverstärkers über die Gates der beiden MOS-Feld-effekttransistoren erfolgt.

摘要翻译： 本发明的目的还在于提供一种 - 指示哪个以最小的延迟时间操作，并且在MOS技术实现，其包括相同类型的场效应晶体管的信号电平转换器 - 特别适合用作快速动态RAM地址缓冲器。 用于将信号电平转换器的本发明的电路被设计成使得其包括由所述转换器通过信号电平转换器控制从所述内部中的冲击电流电平的外部数字信号的差动放大器的方法形成的动作电平的偏差时指示所述差信号的半导体集成电路的数字信号要被加载，和 用于控制动态供电，并设置有两个信号输出端输出电路部分。 信号电平转换器的输出电路部包括两个位于在和两个MOS场效应晶体管，其源极连接中每一个的形式在两个信号输出中的一个，并连接到两个RS触发器中的每一个的同相输出的基准电位RS触发器。 两个MOS场效应晶体管的漏极端子通常由辅助信号计时，而从通过两个MOS场效应晶体管的栅极上的差分放大器的一侧的输出电路的充电进行。

公开(公告)号：EP0068645A2

公开(公告)日：1983-01-05

申请号：EP82302774.3

申请日：1982-05-28

申请人： Hitachi, Ltd.

发明人： Itoh, Kiyoo ,  Hori, Ryoichi

IPC分类号： G11C5/06 ,  G11C11/408 ,  G11C11/409

CPC分类号： G11C11/4096 ,  G11C5/06 ,  G11C5/063 ,  G11C11/4087 ,  G11C11/4097

摘要： A semiconductor memory having a structure wherein each of data lines [D 0 ] intersecting word lines (W i ) is divided into a plurality of sub lines in its lengthwise direction, memory cells (MC) are arranged at the points of intersection between the divided sub lines and the word lines, common input/output lines (1/0) are arranged in common to a plurality of such sub lines, the common input/output lines and the plurality of sub lines are respectively connected by switching elements (SW), and the switching elements are connected to a decoder (Y) through control lines (YC) and are selectively driven by control signals (0y) generated from the decoder.

公开(公告)号：EP0056240A2

公开(公告)日：1982-07-21

申请号：EP82100030.4

申请日：1982-01-05

申请人： NEC CORPORATION

发明人： Watanabe, Hiroshi

IPC分类号： G11C8/00

CPC分类号： G11C11/4087 ,  G11C8/04 ,  G11C11/4085

摘要： An improved memory device operable at a high speed and with a small power consumption is disclosed. The memory device comprises memory cells arrayed in rows and columns, a row decoder for selecting the rows, a column decoder for selecting columns, a shift register arranged in parallel with the column decoder, first control means for operatively enabling the shift register and second control means for suppressing the operation of the column decoder when the shift register is enabled.

摘要翻译： 公开了一种可高速操作且功耗小的改进的存储器装置。 存储装置包括按行和列排列的存储单元，用于选择行的行解码器，用于选择列的列解码器，与列解码器并行布置的移位寄存器，用于可操作地启用移位寄存器的第一控制装置， 用于当移位寄存器被使能时抑制列解码器的操作的装置。

公开(公告)号：EP0017688A1

公开(公告)日：1980-10-29

申请号：EP79302922.4

申请日：1979-12-17

申请人： MOTOROLA, INC.

发明人： Moench, Jerry Dale

IPC分类号： G11C8/00 ,  G11C11/24

CPC分类号： G11C8/10 ,  G11C11/4087 ,  G11C11/418

摘要： A quiet column decoder is provided which is useful in semiconductor memory systems. The quiet column decoder prevents glitches from being coupled into the silicon substrate during the period of time that the sense amplifiers (19) are sensing data on the bit sense lines (17, 18). The quiet column decoder has double clocked NOR gates (25) which allows the address lines (13) to be continuous nonmultiplexed lines. The double clocked NOR gate (25) has two transistors (26, 33) for precharging a first (27) and a second (34) node within the NOR gate. Another transistor (37) is coupled between the second node (34) and a voltage reference terminal (36) to serve as an enabling device for the NOR gate (25). The first node of the NOR gate serves as an output for the column decoder.

公开(公告)号：EP3374994A1

公开(公告)日：2018-09-19

申请号：EP16864817.8

申请日：2016-11-07

申请人： Invensas Corporation

发明人： SUN, Zhuowen ,  CHEN, Yong ,  BANG, Kyong-Mo

IPC分类号： G11C11/408 ,  G11C5/06 ,  G11C8/18 ,  G11C11/409 ,  H01L23/02 ,  H01L23/64 ,  H01L25/065 ,  H01L25/18

CPC分类号： G11C11/4087 ,  G11C5/063 ,  G11C8/18 ,  G11C11/409 ,  H01L23/02 ,  H01L23/3128 ,  H01L23/64 ,  H01L25/0652 ,  H01L25/18 ,  H01L2224/0401 ,  H01L2224/04042 ,  H01L2224/05548 ,  H01L2224/06135 ,  H01L2224/06136 ,  H01L2224/16227 ,  H01L2224/32145 ,  H01L2224/32225 ,  H01L2224/48227 ,  H01L2224/4824 ,  H01L2224/73204 ,  H01L2224/73215 ,  H01L2224/73265 ,  H01L2924/15311 ,  H01L2924/00012 ,  H01L2924/00

摘要： A microelectronic assembly can include an address bus comprising a plurality of signal conductors each passing sequentially through first, second, third, and fourth connection regions, and first and second microelectronic packages. The first microelectronic package can include first and second microelectronic elements, and the second microelectronic package can include third and fourth microelectronic elements. Each microelectronic element can be electrically coupled to the address bus via the respective connection region. An electrical characteristic between the first and second connection regions can be within a same tolerance of the electrical characteristic between the second and third connection regions.

公开(公告)号：EP3268965A1

公开(公告)日：2018-01-17

申请号：EP16762198.6

申请日：2016-03-04

申请人： Micron Technology, Inc.

发明人： HUSH, Glen E. ,  PINNEY, David L.

IPC分类号： G11C7/06 ,  G11C7/10

CPC分类号： G06F3/0647 ,  G06F3/0604 ,  G06F3/0673 ,  G11C5/025 ,  G11C7/06 ,  G11C7/065 ,  G11C7/1006 ,  G11C7/1012 ,  G11C11/4087 ,  G11C11/4091 ,  G11C11/4093 ,  G11C11/4094 ,  G11C11/4096 ,  G11C11/4097 ,  G11C2207/10 ,  G11C2207/104

摘要： The present disclosure includes apparatuses and methods for data movement. An example apparatus comprises a memory device. The memory device includes an array of memory cells and sensing circuitry coupled to the array via a plurality of sense lines. The sensing circuitry includes a sense amplifier and a compute component coupled to a sense line and configured to implement operations. A controller in the memory device is configured to couple to the array and sensing circuitry. A shared I/O line in the memory device is configured to couple a source location and a destination location.

公开(公告)号：EP3243137A1

公开(公告)日：2017-11-15

申请号：EP16735388.7

申请日：2016-01-07

申请人： Micron Technology, Inc.

发明人： WHEELER, Kyle B. ,  MURPHY, Richard C. ,  MANNING, Troy A. ,  KLEIN, Dean A.

IPC分类号： G06F12/02 ,  G06F9/30 ,  G11C7/06

CPC分类号： G06F9/3877 ,  G06F15/7821 ,  G11C7/06 ,  G11C7/065 ,  G11C7/1006 ,  G11C7/1036 ,  G11C11/4087 ,  G11C11/4096

摘要： Examples of the present disclosure provide apparatuses and methods related to generating and executing a control flow. An example apparatus can include a first device configured to generate control flow instructions, and a second device including an array of memory cells, an execution unit to execute the control flow instructions, and a controller configured to control an execution of the control flow instructions on data stored in the array.

公开(公告)号：EP1535162B1

公开(公告)日：2017-10-25

申请号：EP03817282.1

申请日：2003-06-26

申请人： Rambus Inc.

发明人： PEREGO, Richard, E. ,  STARK, Donald, C. ,  WARE, Frederick, A.

IPC分类号： G06F12/04 ,  G06F12/06 ,  G06F12/08

CPC分类号： G06F13/1678 ,  G06F12/04 ,  G06F12/06 ,  G06F12/0646 ,  G06F13/1657 ,  G06F13/4022 ,  G11C5/02 ,  G11C5/025 ,  G11C5/04 ,  G11C5/06 ,  G11C5/063 ,  G11C7/1006 ,  G11C7/1045 ,  G11C7/1048 ,  G11C7/106 ,  G11C7/1072 ,  G11C7/1087 ,  G11C8/06 ,  G11C11/4087 ,  G11C11/4097 ,  G11C2207/105 ,  G11C2207/108 ,  H05K1/117 ,  H05K1/14 ,  H05K2201/09954 ,  H05K2201/10189 ,  Y02D10/14

摘要： Described is a memory system in which the memory core organization changes with device width. The number of physical memory banks accessed reduces with device width, resulting in reduced power usage for relatively narrow memory configurations. Increasing the number of logic memory banks for narrow memory widths reduces the likelihood of bank conflicts, and consequently improves speed performance.

公开(公告)号：EP2888740A4

公开(公告)日：2016-04-13

申请号：EP13830579

申请日：2013-08-20

申请人： MICRON TECHNOLOGY INC

发明人： TANZAWA TORU

IPC分类号： G11C8/12 ,  G11C7/02 ,  G11C8/10 ,  G11C8/16 ,  G11C8/18

CPC分类号： G11C8/10 ,  G11C7/00 ,  G11C7/02 ,  G11C8/12 ,  G11C8/16 ,  G11C8/18 ,  G11C11/4087 ,  G11C13/0004 ,  G11C13/003

摘要： Apparatuses and methods involving accessing distributed sub-blocks of memory cells are described. In one such method, distributed sub-blocks of memory cells in a memory array are enabled to be accessed at the same time. Additional embodiments are described.

摘要翻译： 描述了访问存储器单元的分布式子块的装置和方法。 在一种这样的方法中，能够同时访问存储器阵列中的存储器单元的分布式子块。 描述了另外的实施例。