Cavity package with pre-molded substrate
    2.
    发明公开
    Cavity package with pre-molded substrate 审中-公开
    带预成型基材的腔体包装

    公开(公告)号:EP2843698A3

    公开(公告)日:2015-04-01

    申请号:EP14182490.4

    申请日:2014-08-27

    发明人: Fan, Chun Ho

    摘要: A cavity package is set forth along with a method of manufacturing thereof. The method comprises applying a selective plating resist to a metallic substrate in a pattern to expose portions for a ring, tie bars, die attach pad and input/output wire bonding pads; elective depositing of metal plating using the selective plating resist; removing the selective metal plating resist; applying a selective etching resist to the substrate; selectively etching portions of the substrate not covered by the selective etching resist; stripping away the selective etching resist; pre-molding a leadframe to the substrate so as to surround the die attach pad portion; etching the tie bars away from the bottom surface of the substrate; attaching a semiconductor device die to the die attach pad; wire bonding the semiconductor device to the input/output wire bonding pads; and attaching a cap to the ring portion of the substrate and the die attach pad to protect the wire bonded semiconductor device die and permit electrical grounding.

    摘要翻译: 阐述了一种空腔封装及其制造方法。 该方法包括将选择性抗镀层以图案施加到金属衬底上以暴露环,连接条,管芯附着焊盘和输入/输出导线焊盘的部分; 使用选择性抗镀剂选择性沉积金属镀层; 去除选择性金属电镀抗蚀剂; 将选择性抗蚀剂涂覆到基板上; 选择性地蚀刻未被选择性抗蚀剂覆盖的基板部分; 剥去选择性抗蚀剂; 将引线框架预先模制到衬底以便围绕管芯附接垫部分; 将连接条从基底的底表面上蚀刻掉; 将半导体器件管芯附接到管芯附连焊盘; 将半导体器件引线键合到输入/输出引线键合焊盘; 以及将帽附接到衬底的环形部分和管芯附连垫以保护引线接合的半导体器件管芯并允许电接地。

    Cavity package with pre-molded substrate
    4.
    发明公开
    Cavity package with pre-molded substrate 审中-公开
    Hohlraumpaket mit vorgeformtem Substrat

    公开(公告)号:EP2843698A2

    公开(公告)日:2015-03-04

    申请号:EP14182490.4

    申请日:2014-08-27

    发明人: Fan, Chun Ho

    IPC分类号: H01L23/047 H01L23/10

    摘要: A cavity package is set forth along with a method of manufacturing thereof. The method comprises applying a selective plating resist to a metallic substrate in a pattern to expose portions for a ring, tie bars, die attach pad and input/output wire bonding pads; elective depositing of metal plating using the selective plating resist; removing the selective metal plating resist; applying a selective etching resist to the substrate; selectively etching portions of the substrate not covered by the selective etching resist; stripping away the selective etching resist; pre-molding a leadframe to the substrate so as to surround the die attach pad portion; etching the tie bars away from the bottom surface of the substrate; attaching a semiconductor device die to the die attach pad; wire bonding the semiconductor device to the input/output wire bonding pads; and attaching a cap to the ring portion of the substrate and the die attach pad to protect the wire bonded semiconductor device die and permit electrical grounding.

    摘要翻译: 与其制造方法一起阐述了空腔包装。 该方法包括以图案向金属基底施加选择性电镀抗蚀剂,以露出用于环,连接条,管芯附着垫和输入/输出引线接合焊盘的部分; 使用选择性电镀抗蚀剂选择性沉积金属电镀; 去除选择性金属电镀抗蚀剂; 向所述基底施加选择性抗蚀剂; 选择性地蚀刻未被选择性蚀刻抗蚀剂覆盖的衬底的部分; 剥离选择性抗蚀剂; 将引线框预先模制到基板以围绕芯片附接焊盘部分; 将连接条蚀刻离开基板的底表面; 将半导体器件管芯附接到管芯附接焊盘; 将半导体器件引线接合到输入/输出引线接合焊盘; 并且将盖附接到基板的环部分和管芯附接垫以保护引线接合半导体器件管芯并允许电接地。