公开(公告)号：EP2733727B1

公开(公告)日：2016-08-24

申请号：EP13756799.6

申请日：2013-04-25

申请人： Huawei Technologies Co., Ltd.

发明人： CHEN, Kai ,  LIU, Zhihua ,  JIANG, Ran

IPC分类号： H01L23/495 ,  H01L21/48 ,  H01L23/498 ,  H01L23/00

CPC分类号： H01L21/4828 ,  H01L21/4825 ,  H01L21/4832 ,  H01L23/3107 ,  H01L23/49517 ,  H01L23/49805 ,  H01L24/48 ,  H01L24/73 ,  H01L24/85 ,  H01L2224/32245 ,  H01L2224/48249 ,  H01L2224/73265 ,  H01L2924/00014 ,  H01L2924/12042 ,  H01L2224/48247 ,  H01L2924/00012 ,  H01L2924/00 ,  H01L2224/45099 ,  H01L2224/45015 ,  H01L2924/207

公开(公告)号：EP3007223A1

公开(公告)日：2016-04-13

申请号：EP15185987.3

申请日：2015-09-21

申请人： International Rectifier Corporation

发明人： Cho, Eung San ,  Clavette, Dan

IPC分类号： H01L23/495 ,  H01L23/66 ,  H02M1/00

CPC分类号： H02M7/003 ,  H01L21/4825 ,  H01L21/4828 ,  H01L21/565 ,  H01L23/3114 ,  H01L23/49562 ,  H01L23/49575 ,  H01L23/66 ,  H01L24/48 ,  H01L28/10 ,  H01L29/16 ,  H01L29/2003 ,  H01L29/7787 ,  H01L29/7801 ,  H01L2224/45147 ,  H01L2224/48091 ,  H01L2224/48137 ,  H01L2224/73265 ,  H01L2924/00014 ,  H01L2924/181 ,  H01L2924/19107 ,  H02M3/158 ,  H02M3/1588 ,  H02M7/217 ,  Y02B70/1466 ,  H01L2924/00012 ,  H01L2924/00 ,  H01L2224/05599 ,  H01L2224/85399

摘要： In one implementation, a semiconductor package includes a first patterned conductive carrier including partially etched segments. The semiconductor package also includes a control FET having a control drain attached to a first partially etched segment of the first patterned conductive carrier. In addition, the semiconductor package includes a sync FET having a sync source and a sync gate attached to respective second and third partially etched segments of the first patterned conductive carrier. The semiconductor package further includes a second patterned conductive carrier having a switch node segment situated over a control source of the control FET and over a sync drain of the sync FET, as well as an inductor coupled between the switch node segment and an output segment of the second patterned conductive carrier.

摘要翻译： 在一个实施方案中，半导体封装包括包括部分蚀刻的段的第一图案化导电载体。 半导体封装还包括具有附接到第一图案化导电载体的第一部分蚀刻段的控制漏极的控制FET。 此外，半导体封装包括具有同步源的同步FET和连接到第一图案化导电载体的相应的第二和第三部分蚀刻段的同步栅极。 半导体封装还包括第二图案化导电载体，其具有位于控制FET的控制源上方的开关节点段，以及位于同步FET的同步漏极之间的电感器，以及耦合在开关节点段和 第二图案化导电载体。

公开(公告)号：EP2887393A2

公开(公告)日：2015-06-24

申请号：EP14004185.6

申请日：2014-12-11

申请人： Broadcom Corporation

发明人： Khan, Rezaur Rahman ,  Zhao, Sam

IPC分类号： H01L23/48 ,  H01L23/498

CPC分类号： H01L25/0655 ,  H01L21/4828 ,  H01L21/4853 ,  H01L21/486 ,  H01L21/768 ,  H01L21/76898 ,  H01L23/3171 ,  H01L23/3192 ,  H01L23/48 ,  H01L23/481 ,  H01L23/49827 ,  H01L23/49838 ,  H01L23/528 ,  H01L24/05 ,  H01L24/13 ,  H01L24/16 ,  H01L2224/0345 ,  H01L2224/0346 ,  H01L2224/05572 ,  H01L2224/056 ,  H01L2224/13 ,  H01L2224/16145 ,  H01L2224/16227 ,  H01L2224/73204 ,  H01L2924/00014

摘要： Systems, apparatuses, and methods provided for semiconductor devices and integrated circuit (IC) packages that include compliant dielectric layers. In a through silicon via interposer or substrate (108), a compliant dielectric material (112) may be added to a surface of silicon material body to form a compliant dielectric layer. The compliant dielectric layer provides a thermal buffer and a stress buffer for a resulting IC package. The compliant dielectric material may be selected such that the coefficient of thermal expansion of the compliant dielectric material approximately matches the coefficient of thermal expansion of the circuit board on which the IC package is mounted. The compliant dielectric material may be selected such that it has a deformability that is greater than the silicon material body. Multiple sub-layers of compliant dielectric material may be used.

摘要翻译： 提供用于包括柔性介电层的半导体器件和集成电路（IC）封装的系统，装置和方法。 在硅通孔中介层或衬底（108）中，可以将柔顺介电材料（112）添加到硅材料主体的表面以形成柔性介电层。 柔性电介质层为所得到的IC封装提供热缓冲器和应力缓冲器。 柔性介质材料可以被选择为使得柔性介质材料的热膨胀系数大致匹配其上安装IC封装的电路板的热膨胀系数。 可以选择适应性介电材料，使得它具有比硅材料体大的可变形性。 可以使用多个柔顺介电材料子层。

公开(公告)号：EP1406300B1

公开(公告)日：2012-02-22

申请号：EP02743870.4

申请日：2002-07-09

申请人： SUMITOMO METAL MINING COMPANY LIMITED

发明人： IITANI, Kazunori ,  HAMADA, Youichirou

IPC分类号： H01L23/50 ,  H01L21/48

CPC分类号： H01L21/4828 ,  H01L21/4821 ,  H01L23/49582 ,  H01L24/45 ,  H01L24/48 ,  H01L2224/45144 ,  H01L2224/48091 ,  H01L2224/48247 ,  H01L2224/48664 ,  H01L2224/85464 ,  H01L2924/01028 ,  H01L2924/01046 ,  H01L2924/01057 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/14 ,  H01L2924/3025 ,  H05K3/3426 ,  H01L2924/00014 ,  H01L2924/00

摘要： The semiconductor device mounting surface and substrate mounting surface of a metallic sheet (1) of a lead frame are plated with palladium (1a). The formed lead part, pad part, no-mounting surfaces, and side faces are not plated. The amount of use of palladium is reduced to the requisite minimum, thus providing an inexpensive lead frame.

公开(公告)号：EP2312630A1

公开(公告)日：2011-04-20

申请号：EP11153697.5

申请日：2002-07-09

申请人： SUMITOMO METAL MINING COMPANY LIMITED

发明人： Itani, Kazunori ,  Hamada, Youichirou

IPC分类号： H01L23/50 ,  H01L21/48

CPC分类号： H01L21/4828 ,  H01L21/4821 ,  H01L23/49582 ,  H01L24/45 ,  H01L24/48 ,  H01L2224/45144 ,  H01L2224/48091 ,  H01L2224/48247 ,  H01L2224/48664 ,  H01L2224/85464 ,  H01L2924/01028 ,  H01L2924/01046 ,  H01L2924/01057 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/14 ,  H01L2924/3025 ,  H05K3/3426 ,  H01L2924/00014 ,  H01L2924/00

摘要： A leadframe is plated with palladium (la) only to a surface of a metal plate (1) on which semiconductors elements are to be mounted and a surface of the metal plate (1) to be placed on a substrate, and is not plated with palladium (la) to lead portions, pad portions, other portions except for the surfaces to be plated and the side surface, of the leadframe, thereby, the amount of use of palladium is reduced to minimum and a cheap leadframe can be provided.

摘要翻译： 引线框架仅镀钯（1a）到其上要安装半导体元件的金属板（1）的表面和金属板（1）的放置在基板上的表面，并且不镀覆 钯（1a）引导部分，焊盘部分，除被镀表面以外的其它部分和侧面，从而将钯的使用量降低到最小，并且可以提供便宜的引线框架。

公开(公告)号：EP1673800B1

公开(公告)日：2007-03-21

申请号：EP04789914.1

申请日：2004-10-01

申请人： Infineon Technologies AG

发明人： BETZ, Bernd ,  DANGELMAIER, Jochen ,  PAULUS, Stefan

IPC分类号： H01L21/00

CPC分类号： H01L23/49582 ,  H01L21/4828 ,  H01L23/49503 ,  H01L2924/0002 ,  H01L2924/00

摘要： A flat conductor frame for fitting with a semiconductor chip (2) and for covering with a plastic mass (4) has a single-piece, metal base body (3) on which an intermediate layer (5) is applied. The intermediate layer (5) has a surface (6) with a matrix of islands (14) of leftover materials having substantially a uniform height and cavities (10) extending therebetween.

公开(公告)号：EP0771519A1

公开(公告)日：1997-05-07

申请号：EP95926151.0

申请日：1995-07-03

申请人： OLIN CORPORATION

发明人： MAHULIKAR, Deepak ,  HOFFMAN, Paul, R. ,  BRADEN, Jeffrey, S.

IPC分类号： H01L23 ,  H01L21 ,  H01L25

CPC分类号： H01L25/0657 ,  H01L21/4828 ,  H01L23/13 ,  H01L23/142 ,  H01L23/24 ,  H01L23/49816 ,  H01L24/48 ,  H01L24/49 ,  H01L25/105 ,  H01L2221/68377 ,  H01L2224/16225 ,  H01L2224/32225 ,  H01L2224/48091 ,  H01L2224/49171 ,  H01L2224/73253 ,  H01L2224/73265 ,  H01L2225/0651 ,  H01L2225/0652 ,  H01L2225/06541 ,  H01L2225/06572 ,  H01L2225/06582 ,  H01L2225/06586 ,  H01L2225/1058 ,  H01L2225/1076 ,  H01L2924/00014 ,  H01L2924/01012 ,  H01L2924/01039 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01087 ,  H01L2924/09701 ,  H01L2924/12044 ,  H01L2924/14 ,  H01L2924/15153 ,  H01L2924/15165 ,  H01L2924/15311 ,  H01L2924/1532 ,  H01L2924/15331 ,  H01L2924/16152 ,  H01L2924/163 ,  H01L2924/181 ,  H01L2924/3025 ,  H01L2224/45099 ,  H01L2924/00012

摘要： There is disclosed components for electronic packaging applications having integral bumps. A leadframe is formed by etching a metallic strip from one side to form outwardly extending, substantially perpendicular integral bumps. The metallic strip is then etched from the opposite side to form individual leads. When the integrally bumped component is an package base, fatigue of solder balls is reduced.

公开(公告)号：EP0646962A1

公开(公告)日：1995-04-05

申请号：EP94910594.4

申请日：1994-04-04

申请人： HITACHI CONSTRUCTION MACHINERY CO., LTD.

发明人： TADA, Nobuhiko ,  MIYANAGI, Naoki ,  SHIMOMURA, Yoshiaki Hitachikenki Chiyoda-house ,  SAKURAI, Shigeyuki Hitachikenki Chiyoda-ryo 1-226 ,  NAGANO, Yoshinari Hitachikenki Chiyoda-house

IPC分类号： H01L23/50 ,  B23K26/00 ,  C23F1/00 ,  H01L21/48

CPC分类号： B23K26/384 ,  B23K26/0619 ,  B23K26/067 ,  B23K26/18 ,  B23K26/382 ,  B23K26/40 ,  B23K2201/35 ,  B23K2203/50 ,  H01L21/4821 ,  H01L21/4828 ,  H01L2924/0002 ,  H05K3/027 ,  H05K3/061 ,  H05K3/202 ,  Y10T29/49121 ,  H01L2924/00

摘要： An object of this invention is to provide a metal sheet processing method and a lead frame processing method which are capable of processing a work to an excellent shape finely with a high dimensional accuracy without being influenced by heat input due to the irradiation of a laser beam. According to the present invention, a metal sheet (101) is coated at both surfaces thereof with photoresist films (1) first, and a laser beam (202) is then applied to the metal sheet (101) through the outer surface of the photoresist film (1) so as to form a plurality of discontinuous through bores (3) in rows with joint portions (6) as unprocessed portions left among the through bores (3). The opened portions (2) formed by the laser beam processing of the photoresist film (1) extend continuously to serve as an etching pattern. The surrounding wall portions (6) are then subjected to etching to remove the same and connect together the through bores (3) formed in rows, whereby clearances (303a) of a predetermined shape are formed. Instead of forming the through bores (3) and joint portions (6) in the metal sheet (101), the steps of forming non-through bores (51) in the metal sheet (101) with joint portions (52) left as unprocessed portions in their bottoms, and then subjecting the resultant product to etching may be taken.

摘要翻译： 本发明的目的是提供一种能够以高尺寸精度细微处理工件，而不受激光束照射引起的热输入的影响的金属片处理方法和引线框处理方法 。 根据本发明，首先在金属片（101）的两个表面上涂覆有光致抗蚀剂膜（1），然后通过光致抗蚀剂的外表面将激光束（202）施加到金属片（101） 膜（1），以便形成多个具有接合部分（6）的不连续贯通孔（3），作为未加工部分留在通孔（3）中。 通过光致抗蚀剂膜（1）的激光束处理形成的开口部分（2）连续延伸以用作蚀刻图案。 然后对周围的壁部（6）进行蚀刻以除去它们，并且将形成的通孔（3）连接在一起，由此形成预定形状的间隙（303a）。 代替在金属板（101）中形成通孔（3）和接合部分（6），在金属板（101）中形成具有未加工的接合部分（52）的非贯通孔（51）的步骤 可以采用其底部的部分，然后对所得产物进行蚀刻。

公开(公告)号：EP0507043A3

公开(公告)日：1992-12-16

申请号：EP92100140.0

申请日：1992-01-07

申请人： SHIPLEY COMPANY INC.

发明人： Harris, Martin J. ,  Ho, Ivan K.

IPC分类号： C23F1/02 ,  C25D5/02

CPC分类号： H01L21/4828 ,  C09D5/4411 ,  C23F1/02 ,  C25D5/022 ,  G03F7/164 ,  H05K3/0079 ,  H05K3/064 ,  H05K3/202

摘要： Method for selective and precise etching and plating of a conductive substrate through electrophoretic deposition of a photoresist composition. The invention enables chemical milling and plating of products useful in high performance applications such as lead frames with lead widths less than 1.0 mil and precisely plated lead faces.

公开(公告)号：EP0507043A2

公开(公告)日：1992-10-07

申请号：EP92100140.0

申请日：1992-01-07

申请人： SHIPLEY COMPANY INC.

发明人： Harris, Martin J. ,  Ho, Ivan K.

IPC分类号： C23F1/02 ,  C25D5/02

CPC分类号： H01L21/4828 ,  C09D5/4411 ,  C23F1/02 ,  C25D5/022 ,  G03F7/164 ,  H05K3/0079 ,  H05K3/064 ,  H05K3/202

摘要： Method for selective and precise etching and plating of a conductive substrate through electrophoretic deposition of a photoresist composition. The invention enables chemical milling and plating of products useful in high performance applications such as lead frames with lead widths less than 1.0 mil and precisely plated lead faces.

摘要翻译： 用于通过光致抗蚀剂组合物的电泳沉积一个导电性基板的选择性和精确的蚀刻和镀覆法。 本发明能够使化学研磨和的在高性能应用中有用的产品电镀：如引线框与引线宽度小于1.0密耳且精确地镀敷引线的面。