公开(公告)号：EP1801151B1

公开(公告)日：2009-04-22

申请号：EP06077248.0

申请日：2006-12-14

Applicant: Delphi Technologies, Inc.

Inventor： Basheer, Rafil A. ,  Bouguettaya, Mohammed ,  Workman, Derek B. ,  Chaudhuri, Arun K.

IPC: C08K7/00 ,  H01L21/56 ,  H01L21/60

CPC classification number: H01L21/563 ,  B82Y30/00 ,  C08K2201/011 ,  H01L23/293 ,  H01L23/295 ,  H01L2224/73203 ,  H01L2224/81801 ,  H01L2924/01019 ,  H01L2924/0102 ,  H01L2924/01025 ,  H01L2924/01046 ,  H01L2924/01057 ,  H01L2924/01063 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01322

公开(公告)号：EP1911784A1

公开(公告)日：2008-04-16

申请号：EP07075767.9

申请日：2007-09-06

Applicant: Delphi Technologies, Inc.

Inventor： Basheer, Rafil A. ,  Workman, Derek B. ,  Bouguettaya, Mohamed

IPC: C08G59/32 ,  C08K3/36 ,  C08K9/06 ,  H01L21/56 ,  H01L21/60 ,  H01L23/29 ,  H01L23/485 ,  H01L23/498

CPC classification number: H01L21/563 ,  C08G59/3227 ,  C08L63/00 ,  H01L23/295 ,  H01L23/296 ,  H01L24/10 ,  H01L24/13 ,  H01L2224/13 ,  H01L2224/13099 ,  H01L2224/16 ,  H01L2224/73203 ,  H01L2224/81193 ,  H01L2224/81801 ,  H01L2224/83192 ,  H01L2924/00011 ,  H01L2924/00014 ,  H01L2924/01006 ,  H01L2924/01015 ,  H01L2924/01019 ,  H01L2924/01027 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01047 ,  H01L2924/01057 ,  H01L2924/01058 ,  H01L2924/0106 ,  H01L2924/01061 ,  H01L2924/01063 ,  H01L2924/0107 ,  H01L2924/01074 ,  H01L2924/01075 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/01322 ,  H01L2924/014 ,  H01L2924/14 ,  H01L2924/19043 ,  C08L2666/54 ,  H01L2924/00 ,  H01L2224/0401

Abstract: A themosettable material having excellent processability, and which cures to form a thermoset composition having a low coefficient of thermal expansion and a high glass transition temperature includes functionalized nanoscopic silica particles dispersed in a curable resin comprising a polyepoxide having at least three epoxide groups per molecule. The composition is useful as an underfill for flip-chip circuit assemblies.

Abstract translation: 具有优异加工性的固化性材料，其固化形成具有低热膨胀系数和高玻璃化转变温度的热固性组合物包括分散在包含每分子具有至少三个环氧基团的聚环氧化物的可固化树脂的官能化纳米二氧化硅颗粒。 该组合物可用作倒装芯片电路组件的底部填充物。

公开(公告)号：EP1628509A3

公开(公告)日：2006-10-04

申请号：EP05076727.6

申请日：2005-07-27

Applicant: Delphi Technologies, Inc.

Inventor： Delheimer, Charles I. ,  Workman, Derek B. ,  Tsai, Jeenhuei S. ,  Walsh, Matthew R. ,  Brandenburg, Scott D. ,  Thompson, Brian D.

IPC: H05K3/28 ,  H05K3/30 ,  H01L23/31 ,  H01L21/56

CPC classification number: H05K3/303 ,  H01L21/563 ,  H01L23/3121 ,  H01L2224/16225 ,  H01L2224/73203 ,  H01L2924/00011 ,  H01L2924/00014 ,  H01L2924/1305 ,  H01L2924/13055 ,  H01L2924/1433 ,  H01L2924/19041 ,  H05K3/284 ,  H05K2201/10674 ,  H05K2201/2036 ,  Y02P70/613 ,  H01L2924/00 ,  H01L2224/0401

Abstract: An electronic module (100) includes a substrate (108), at least one surface mounted integrated circuit (IC) component (110) and an underfill material (122). The substrate (108) includes a plurality of electrically conductive traces (118A,118B), formed on at least one surface of the substrate (108), and the component (110) is electrically coupled to at least one of the conductive traces (118A,118B). The underfill material (122) is positioned between the component (110) and the substrate (108) and provides at least one pedestal that supports the component (110) during encapsulation. The underfill material (122), when cured, maintains the integrity of the electrical connections between the component (110) and the conductive traces (118A,118B).

公开(公告)号：EP1463103A8

公开(公告)日：2004-12-08

申请号：EP04075759.3

申请日：2004-03-09

Applicant: Delphi Technologies, Inc.

Inventor： Workman, Derek B. ,  Chaudhuri, Arun K.

IPC: H01L21/56

CPC classification number: H01L24/27 ,  H01L21/563 ,  H01L24/29 ,  H01L2224/16225 ,  H01L2224/29036 ,  H01L2224/32225 ,  H01L2224/73104 ,  H01L2224/73203 ,  H01L2224/73204 ,  H01L2224/83191 ,  H01L2224/83192 ,  H01L2224/83193 ,  H01L2924/01005 ,  H01L2924/01013 ,  H01L2924/01033 ,  H01L2924/01039 ,  H01L2924/01075 ,  H01L2924/12042 ,  Y10T29/4913 ,  Y10T29/49144 ,  Y10T29/49146 ,  Y10T29/49176 ,  Y10T29/49179 ,  H01L2924/00 ,  H01L2924/3512

Abstract: A process for selectively depositing a filled underfill material (14) onto a die surface without covering solder bumps (12) present on the die (10). The process entails microjetting a polymer matrix material, a filler material, and optionally a fluxing material (22) onto the die surface. Together, the polymer matrix and filler materials define the filled underfill material (14) in which the filler material is dispersed to reduce the coefficient of thermal expansion of the underfill material (14). The resulting underfill material (14) surrounds but does not cover the solder bumps (12). The die (10) is then placed on a substrate (16) on which a second underfill material (26) is present, forming a composite underfill layer (24) that completely fills the space between the die (10) and substrate (16) and forms a fillet (28) on a peripheral wall (30) of the die (10).

公开(公告)号：EP1710265B1

公开(公告)日：2008-01-23

申请号：EP06075734.1

申请日：2006-03-29

Applicant: Delphi Technologies, Inc.

Inventor： Basheer, Rafil A. ,  Workman, Derek B.

IPC: C08G59/40 ,  A61K49/04

CPC classification number: C08G59/24 ,  C08G59/4215 ,  C08G59/5033 ,  C08G59/62 ,  Y10T428/31515

公开(公告)号：EP1801151A1

公开(公告)日：2007-06-27

申请号：EP06077248.0

申请日：2006-12-14

Applicant: Delphi Technologies, Inc.

Inventor： Basheer, Rafil A. ,  Bouguettaya, Mohammed ,  Workman, Derek B. ,  Chaudhuri, Arun K.

IPC: C08K7/00 ,  H01L21/56 ,  H01L21/60

CPC classification number: H01L21/563 ,  B82Y30/00 ,  C08K2201/011 ,  H01L23/293 ,  H01L23/295 ,  H01L2224/73203 ,  H01L2224/81801 ,  H01L2924/01019 ,  H01L2924/0102 ,  H01L2924/01025 ,  H01L2924/01046 ,  H01L2924/01057 ,  H01L2924/01063 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01322

Abstract: Disclosed is a method for making a low CTE curable composition. In one embodiment, the method comprises mixing together (i) from 0.1 to 60.0 % by weight of a nanoparticle composition and (ii) from 20.0 to 90.0 % by weight of a curable binder to provide a premixture, based on the total weight of the premixture, and subjecting the premixture to high shear forces until the nanoparticle composition (i) is sufficiently dispersed in the curable binder (ii) to provide a curable composition. It has been found that the nanoparticle composition (i) must be at least one of (a) a strongly functionalized nanoparticle composition (i) having no more than 25 mole % functionalization, (b) a weakly functionalized nanoparticle composition having from 1 to 100 mole % functionalization, (c) a nonfunctionalized nanoparticle composition, or (d) mixtures thereof.

公开(公告)号：EP1705968A2

公开(公告)日：2006-09-27

申请号：EP06075577.4

申请日：2006-03-10

Applicant: Delphi Technologies, Inc.

Inventor： Fairchild, Ray M. ,  Sarma, Dwasasi H. ,  Workman, Derek B. ,  Harshbarger, Daniel R.

IPC: H05K1/14 ,  H05K1/18

CPC classification number: H01L23/142 ,  H01L21/563 ,  H01L23/5385 ,  H01L2224/16225 ,  H01L2224/32225 ,  H01L2224/48227 ,  H01L2224/73204 ,  H01L2924/00011 ,  H01L2924/00014 ,  H01L2924/09701 ,  H01L2924/1305 ,  H01L2924/13055 ,  H01L2924/15311 ,  H01L2924/30107 ,  H05K1/0306 ,  H05K1/053 ,  H05K1/141 ,  H05K3/284 ,  H05K3/3436 ,  H05K2201/0212 ,  H05K2201/10977 ,  H01L2924/00 ,  H01L2224/0401

Abstract: An electronic assembly (100) includes a first substrate (102) and a second substrate (122). The first substrate (102) includes a first surface having a first plurality of conductive traces (106) formed on an electrically non-conductive layer (104). The second substrate (122) includes a first surface having a second plurality of conductive traces (126) formed thereon and a second surface having a third plurality of conductive traces (124) formed thereon. A first electronic component (132) is electrically coupled to one or more of the plurality of conductive traces (126) on the first surface of the second substrate (122). At least one of a plurality of conductive interconnects (108) is incorporated within each solder joint that electrically couples one or more of the conductive traces (124) formed on the second surface of the second substrate (122) to one or more of the conductive traces (106) formed on the first substrate (102).

Abstract translation: 电子组件（100）包括第一基板（102）和第二基板（122）。 第一衬底（102）包括具有形成在非导电层（104）上的第一多个导电迹线（106）的第一表面。 第二衬底（122）包括具有形成在其上的第二多个导电迹线（126）的第一表面和在其上形成有第三多个导电迹线（124）的第二表面。 第一电子部件（132）电耦合到第二基板（122）的第一表面上的多个导电迹线（126）中的一个或多个。 多个导电互连件（108）中的至少一个被并入每个焊接接头内，将形成在第二衬底（122）的第二表面上的一个或多个导电迹线（124）电耦合到一个或多个导电 形成在第一基板（102）上的迹线（106）。

公开(公告)号：EP1628509A2

公开(公告)日：2006-02-22

申请号：EP05076727.6

申请日：2005-07-27

Applicant: Delphi Technologies, Inc.

Inventor： Delheimer, Charles I. ,  Workman, Derek B. ,  Tsai, Jeenhuei S. ,  Walsh, Matthew R. ,  Brandenburg, Scott D. ,  Thompson, Brian D.

IPC: H05K3/28 ,  H05K3/30

CPC classification number: H05K3/303 ,  H01L21/563 ,  H01L23/3121 ,  H01L2224/16225 ,  H01L2224/73203 ,  H01L2924/00011 ,  H01L2924/00014 ,  H01L2924/1305 ,  H01L2924/13055 ,  H01L2924/1433 ,  H01L2924/19041 ,  H05K3/284 ,  H05K2201/10674 ,  H05K2201/2036 ,  Y02P70/613 ,  H01L2924/00 ,  H01L2224/0401

Abstract: An electronic module (100) includes a substrate (108), at least one surface mounted integrated circuit (IC) component (110) and an underfill material (122). The substrate (108) includes a plurality of electrically conductive traces (118A,118B), formed on at least one surface of the substrate (108), and the component (110) is electrically coupled to at least one of the conductive traces (118A,118B). The underfill material (122) is positioned between the component (110) and the substrate (108) and provides at least one pedestal that supports the component (110) during encapsulation. The underfill material (122), when cured, maintains the integrity of the electrical connections between the component (110) and the conductive traces (118A,118B).

Abstract translation: 电子模块（100）包括衬底（108），至少一个表面安装集成电路（IC）部件（110）和底部填充材料（122）。 衬底（108）包括形成在衬底（108）的至少一个表面上的多个导电迹线（118A，118B），并且部件（110）电耦合到导电迹线（118A）中的至少一个 ，118B）。 底部填充材料（122）位于部件（110）和基板（108）之间，并且提供至少一个在封装期间支撑部件（110）的基座。 底部填充材料（122）在固化时保持部件（110）和导电迹线（118A，118B）之间的电连接的完整性。

公开(公告)号：EP1719789B1

公开(公告)日：2008-10-01

申请号：EP06075878.6

申请日：2006-04-13

Applicant: Delphi Technologies, Inc.

Inventor： Basheer, Rafil A. ,  Workman, Derek B. ,  Chaudhuri, Arun K. ,  Bouguettaya, Mohamed

IPC: C08G59/62 ,  C08G59/68 ,  C08G83/00 ,  C09D163/00

CPC classification number: C08L101/005 ,  C08L63/00 ,  C08L67/04 ,  C08L2666/14

公开(公告)号：EP1705968A3

公开(公告)日：2008-06-04

申请号：EP06075577.4

申请日：2006-03-10

Applicant: Delphi Technologies, Inc.

Inventor： Fairchild, Ray M. ,  Sarma, Dwasasi H. ,  Workman, Derek B. ,  Harshbarger, Daniel R.

IPC: H05K1/14 ,  H05K1/18 ,  H01L23/538

CPC classification number: H01L23/142 ,  H01L21/563 ,  H01L23/5385 ,  H01L2224/16225 ,  H01L2224/32225 ,  H01L2224/48227 ,  H01L2224/73204 ,  H01L2924/00011 ,  H01L2924/00014 ,  H01L2924/09701 ,  H01L2924/1305 ,  H01L2924/13055 ,  H01L2924/15311 ,  H01L2924/30107 ,  H05K1/0306 ,  H05K1/053 ,  H05K1/141 ,  H05K3/284 ,  H05K3/3436 ,  H05K2201/0212 ,  H05K2201/10977 ,  H01L2924/00 ,  H01L2224/0401

Abstract: An electronic assembly (100) includes a first substrate (102) and a second substrate (122). The first substrate (102) includes a first surface having a first plurality of conductive traces (106) formed on an electrically non-conductive layer (104). The second substrate (122) includes a first surface having a second plurality of conductive traces (126) formed thereon and a second surface having a third plurality of conductive traces (124) formed thereon. A first electronic component (132) is electrically coupled to one or more of the plurality of conductive traces (126) on the first surface of the second substrate (122). At least one of a plurality of conductive interconnects (108) is incorporated within each solder joint that electrically couples one or more of the conductive traces (124) formed on the second surface of the second substrate (122) to one or more of the conductive traces (106) formed on the first substrate (102).