摘要:
Die Erfindung bezieht sich auf ein Verfahren zum Ausbilden zumindest eines lokalen Kontaktbereichs eines Substrats eines elektrischen Bauelementes zum Kontaktieren des Kontaktbereichs mit einem Verbinder, wobei das Substrat kontaktseitig mit einer aus Metall bestehenden oder Metall enthaltenden porösen Schicht versehen ist. Um einen mechanisch haltbaren elektrisch einwandfrei lötbaren Kontaktbereich zur Verfügung zu stellen, wird vorgeschlagen, dass die poröse Schicht in dem auszubildenden Kontaktbereich verdichtet und/oder entfernt wird.
摘要:
Disclosed is a curable composition having a low CTE. In one embodiment, a curable composition is disclosed that comprises (i) a binder comprising at least one epoxy compound of the structure:
X-((CH 2 ) m -(N)-((CH 2 ) n -(Z)) 2 ) p
wherein X is an aromatic ring or a six membered cycloaliphatic ring, m is from about 0 to about 2, n is from about 1 to about 3, Z is an epoxy group of empirical formula: C 2 H 3 O, p is a number from about 2 to about 3, and (ii) a cross-linking agent comprising at least one polyamine. This curable composition is characterized by a CTE of no more than 60 ppm/°C when cured for a time of from about 20 to about 60 minutes at temperature of from about 100 to 240°C. Also disclosed are methods of making integrated circuits and integrated circuits made there from, especially flip chips.
摘要:
A nitride semiconductor light-emitting device includes a layered portion emitting light on a substrate. The layered portion includes an n-type semiconductor layer, an active layer, and a p-type semiconductor layer. The periphery of the layered portion is inclined, and the surface of the n-type semiconductor layer is exposed at the periphery. An n electrode is disposed on the exposed surface of the n-type semiconductor layer. This device structure can enhance the emission efficiency and the light extraction efficiency.
摘要:
Method for bonding a chip (20) to a chip carrier (21) including arranging the chip (20) in alignment with the chip carrier (21) to form a chip stack. First bond area situated on the chip at an interface between the chip (20) and the chip carrier (21) in contact with second bond area situated on the chip carrier (21) at the interface. Projecting a laser beam (25) through the chip (20) and/or the chip carrier (21), the laser beam (25) impinging on the first bond area and/or the second bond area melting the first bond area and/or the second bond area to form a bond electrically coupling the chip (20) and the chip carrier (21). A device including a chip (20) having a first bond area situated on a chip carrier side of the chip and a chip carrier (21) having a second bond area situated on a chip side of the chip carrier (21). The contact area less than about 40 µm 2 . A system for bonding a chip (20) to a chip carrier (21) including a laser (25) and an aperture for holding a chip stack in alignment. The chip stack includes a chip (20) and a chip carrier (21). The laser (25) is directed and/or focused by the aperture. The laser projects a laser beam through the chip (20) and /or the chip carrier (21) which impinges on the first bond area and/or the second bond area. The first bond area situated on a chip carrier side of the chip (20) and the second bond area situated on a chip side of the chip carrier (21). The first bond area area contacting the second bond area. The first bond area is bonded to the second bond area by the laser beam (25) impinging on the first bond area and/or the second bond area.
摘要:
A package for a semiconductor chip having the following features: (a) a power-supply layer, a ground layer, and a signal layer are formed in multilayer through intermediate layers including insulating layers; (b) the power-supply layer and ground layer each comprise an inner lead region exposed from the intermediate layers, an outer lead region, and a conductive region sandwiched by these two regions and covered by the intermediate layers; and (c) the conductive regions of the power-supply layer and ground layer consist of planar conductive members. The self-inductances of the power-supply and ground layers of this package are low, and the capacitance of the capacitor formed by these layers is low. Therefore, the noise of the power-supply system is little.
摘要:
Wire-bonding of a semiconductor device designed in accordance with the CAD system is implemented on the basis of bonding data obtained by making use of the design data in the CAD system. For the design data in the CAD system, coordinate data of the bonding pads and the lead frames and wiring information therebetween are used. Since ordinarily the coordinate system in the CAD system and the coordinate system in the wire-bonding apparatus are not equal to each other, coordinate transformation is applied to the bonding data obtained from the CAD system. The data thus transformed is delivered to the bonding unit. Since there is employed a scheme to utilize the design data in the CAD system, the necessity of inputting bonding data by an operator is eliminated, thus making it possible to carry out bonding work free from an error in a short time.
摘要:
A pressure application technique is provided that enables two objects to be pressurized (e.g., objects to be bonded) to be positioned with greater accuracy before having pressure applied thereto. The objects to be pressurized are moved relative to each other in a Z direction such that the objects are brought into contact with each other (step S13). Then, a horizontal positional shift ”D between the objects to be pressurized is measured in the contact state of the objects to be pressurized (step S14). Thereafter, positioning of the objects to be pressurized is again performed by moving the objects to be pressurized relative to each other in the horizontal direction, as a result of which the positional shift ”D is corrected (step S17).
摘要:
[Issues to be solved] Second bonding failures caused attached oxide of additive elements on high purity Au bonding wire are to be dissolved. [Solution means] Au alloy bonding wires comprising: 5 - 100 wt ppm Mg, 5 - 20 wt ppm In, 5 - 20 wt ppm Al, 5 - 20 wt ppm Yb, and Au residual is more than 99.995 wt % purity, and adding 5 - 20 wt ppm Ca, and for these alloys adding at least more than one element among 5 - 20 wt ppm La, 5 - 20 wt ppm Lu, 5 - 100 wt ppm Sn, 5 - 100 wt ppm Sr to the alloy, and/or, more over, adding 0.01 - 1.2 wt % Pd to these alloys. Bonding wire, which contains these trace additive elements .do not cause of disturbance by accumulated contamination, because of contamination, which formed at ball formation by micro discharge and at the first bonding to attached on tip of capillary, transferring to the wire at second bonding.