公开(公告)号：EP3146561A2

公开(公告)日：2017-03-29

申请号：EP15725962.3

申请日：2015-05-18

申请人： Microchip Technology Incorporated

发明人： DIX, Greg ,  MELCHER, Roger ,  KLINE, Harold

IPC分类号： H01L23/485 ,  H01L23/528 ,  H01L23/482 ,  H01L23/495

CPC分类号： H01L23/49513 ,  H01L23/3114 ,  H01L23/3171 ,  H01L23/4824 ,  H01L23/4951 ,  H01L23/49541 ,  H01L23/49562 ,  H01L23/49575 ,  H01L23/528 ,  H01L24/05 ,  H01L24/13 ,  H01L24/14 ,  H01L24/16 ,  H01L24/48 ,  H01L24/49 ,  H01L2224/05553 ,  H01L2224/05554 ,  H01L2224/13014 ,  H01L2224/13022 ,  H01L2224/13028 ,  H01L2224/131 ,  H01L2224/1319 ,  H01L2224/14133 ,  H01L2224/1613 ,  H01L2224/16245 ,  H01L2224/48245 ,  H01L2224/49171 ,  H01L2924/00014 ,  H01L2924/1305 ,  H01L2924/19107 ,  H01L2924/014 ,  H01L2924/0665 ,  H01L2924/0781 ,  H01L2924/00012 ,  H01L2224/45099

摘要： A semiconductor power chip has a semiconductor power device formed on a semiconductor die; wherein the semiconductor power device comprises an array of conductive contact elements; a passivation layer formed over the plurality of conductive contact elements, the passivation layer comprising passivation openings over a plurality of the conductive contact elements; and an array of conductive bumps including one or more interconnection bumps, wherein each interconnection bump is formed over the passivation layer and extends into at least two of the passivation openings and into contact with at least two underlying conductive contact elements to thereby provide a conductive coupling between the at least two underlying conductive contact elements.

摘要翻译： 半导体功率芯片具有形成在半导体晶片上的半导体功率器件; 其中所述半导体功率器件包括导电接触元件阵列; 形成在所述多个导电接触元件上的钝化层，所述钝化层包括多个所述导电接触元件上的钝化开口; 以及包括一个或多个互连凸块的导电凸块阵列，其中每个互连凸块形成在钝化层之上并且延伸到至少两个钝化开口中并与至少两个下面的导电接触元件接触，从而提供导电耦合 在所述至少两个下面的导电接触元件之间。

公开(公告)号：EP2737539A2

公开(公告)日：2014-06-04

申请号：EP12750895.0

申请日：2012-07-23

申请人： Microchip Technology Incorporated

发明人： DIX, Gregory ,  MCKEEN, Leighton, E. ,  LIVINGSTON, Ian ,  MELCHER, Roger ,  BRAITHWAITE, Rohan

IPC分类号： H01L29/78 ,  H01L29/08 ,  H01L29/36 ,  H01L29/10 ,  H01L23/544 ,  H01L21/336 ,  H01L29/423 ,  H01L21/266

CPC分类号： H01L29/7816 ,  H01L23/544 ,  H01L29/0847 ,  H01L29/0878 ,  H01L29/42368 ,  H01L29/66659 ,  H01L29/66681 ,  H01L29/7835 ,  H01L2223/54426 ,  H01L2223/54453 ,  H01L2924/0002 ,  H01L2924/00

摘要： At least one N-well implant having a different doping level is formed in a silicon substrate by first etching the substrate with an alignment target for aligning future process masks thereto. This alignment target is outside of any active device area. By using at least one N-well implant having a different doping level in combination with the substrate, a graded junction in the drift area of a metal oxide semiconductor (MOS) field effect transistor (FET) can be created and a pseudo Ldd structure may be realized thereby.

公开(公告)号：EP2973691A1

公开(公告)日：2016-01-20

申请号：EP14711892.1

申请日：2014-03-01

申请人： Microchip Technology Incorporated

发明人： DIX, Gregory ,  MELCHER, Roger

IPC分类号： H01L23/485 ,  H01L23/482 ,  H01L23/495 ,  H01L23/31 ,  H01L25/065 ,  H01L21/60

CPC分类号： H01L23/4952 ,  H01L23/3171 ,  H01L23/4824 ,  H01L23/4951 ,  H01L23/49562 ,  H01L23/49575 ,  H01L24/05 ,  H01L24/11 ,  H01L24/13 ,  H01L24/14 ,  H01L24/16 ,  H01L24/17 ,  H01L24/48 ,  H01L24/49 ,  H01L24/81 ,  H01L2224/0401 ,  H01L2224/05554 ,  H01L2224/05567 ,  H01L2224/05647 ,  H01L2224/1148 ,  H01L2224/13014 ,  H01L2224/13021 ,  H01L2224/13082 ,  H01L2224/131 ,  H01L2224/13147 ,  H01L2224/1329 ,  H01L2224/133 ,  H01L2224/1403 ,  H01L2224/14133 ,  H01L2224/14163 ,  H01L2224/16112 ,  H01L2224/16245 ,  H01L2224/17107 ,  H01L2224/48247 ,  H01L2224/49171 ,  H01L2224/81191 ,  H01L2224/81801 ,  H01L2224/8185 ,  H01L2924/00014 ,  H01L2924/1305 ,  H01L2924/1306 ,  H01L2924/014 ,  H01L2924/0665 ,  H01L2924/00 ,  H01L2224/05552 ,  H01L2224/45099 ,  H01L2224/05599

摘要： A semiconductor power chip, may have a semiconductor die having a power device fabricated on a substrate thereof, wherein the power device has at least one first contact element, a plurality of second contact elements and a plurality of third contact elements arranged on top of the semiconductor die; and an insulation layer disposed on top of the semiconductor die and being patterned to provide openings to access the plurality of second and third contact elements and the at least one first contact element.

摘要翻译： 一种半导体功率芯片，可以具有与具有在其上制造一个衬底的功率器件，worin的功率器件的半导体具有至少一个第一接触元件，第二接触元件的多元化和布置在顶部第三接触元件的多元性 半导体管芯; 和绝缘层上设置在半导体的顶部和被图案化，以提供开口以访问第二和第三接触元件的多元性和所述至少一个第一接触元件。

公开(公告)号：EP2965355A1

公开(公告)日：2016-01-13

申请号：EP14709120.1

申请日：2014-02-24

申请人： Microchip Technology Incorporated

发明人： DIX, Gregory ,  KLINE, Harold ,  GRIMM, Dan ,  MELCHER, Roger ,  WILLIAMS, Jacob, L.

IPC分类号： H01L23/522 ,  H01L29/78

CPC分类号： H01L29/78 ,  H01L23/4824 ,  H01L23/5226 ,  H01L29/66477 ,  H01L2924/0002 ,  H01L2924/00

摘要： A power MOS field effect transistor (FET) has a plurality of transistor cells, each cell having a source region and a drain region to be contacted through a surface of a silicon wafer die. A first dielectric layer is disposed on the surface of the silicon wafer die and a plurality of grooves are formed in the first dielectric layer above the source regions and drain regions, respectively and filled with a conductive material. A second dielectric layer is disposed on a surface of the first dielectric layer and has openings to expose contact areas to said grooves. A metal layer is disposed on a surface of the second dielectric layer and filling the openings, wherein the metal layer is patterned and etched to form separate metal wires connecting each drain region and each source region of the plurality of transistor cells, respectively through the grooves.