公开(公告)号：EP2187436A4

公开(公告)日：2013-11-20

申请号：EP09773082

申请日：2009-02-17

Applicant: OMRON TATEISI ELECTRONICS CO

Inventor： ONO KAZUYUKI ,  TANAKA YOSHIO ,  NAKAJIMA KIYOSHI ,  KURATANI NAOTO ,  MAEKAWA TOMOFUMI

IPC: H01L23/00 ,  B81C1/00

CPC classification number: H01L23/055 ,  B81B2201/0257 ,  B81C1/00269 ,  B81C2203/0109 ,  B81C2203/019 ,  B81C2203/032 ,  H01L23/552 ,  H01L24/27 ,  H01L24/29 ,  H01L24/32 ,  H01L24/48 ,  H01L24/73 ,  H01L24/83 ,  H01L2224/27013 ,  H01L2224/2919 ,  H01L2224/29191 ,  H01L2224/32014 ,  H01L2224/32225 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/484 ,  H01L2224/73265 ,  H01L2224/83051 ,  H01L2224/83192 ,  H01L2224/83855 ,  H01L2924/00014 ,  H01L2924/01004 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01047 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/01322 ,  H01L2924/014 ,  H01L2924/0665 ,  H01L2924/10158 ,  H01L2924/1433 ,  H01L2924/1461 ,  H01L2924/16152 ,  H01L2924/3025 ,  H01L2924/0715 ,  H01L2924/00 ,  H01L2224/45099 ,  H01L2224/05599 ,  H01L2924/00012

Abstract: On the upper surface of a substrate (52) (printed substrate), a pad (55), which is to be used for die bonding and has a surface of a conductive pattern section (61a) coated with an inorganic material (61b) such as Au plating, is arranged. A solder resist (67) is applied onto the center portion of the pad (55), and the inorganic material (61b) is exposed from the outer circumference portion of the pad (55). A semiconductor element (53) is adhered and fixed onto the pad by a die bonding resin. The pad (55) and other adjacent conductive patterns are separated by a groove (60), and the solder resist (67) covering the conductive pattern is configured not to be brought into contact with the pad (55).

Abstract translation: 在基板（52）（印刷基板）的上表面上形成有用于芯片接合的焊盘（55），该焊盘（55）具有涂覆有无机材料（61b）的导电图案部分（61a）的表面 如Au镀层一样。 在焊盘55的中央部涂布阻焊剂67，无机材料61b从焊盘55的外周部露出。 半导体元件（53）通过芯片接合树脂粘附并固定到焊盘上。 焊盘55和其他相邻的导电图案被槽60分开，并且覆盖导电图案的阻焊剂67被配置为不与焊盘55接触。

公开(公告)号：EP2187435A4

公开(公告)日：2013-11-13

申请号：EP09773081

申请日：2009-02-16

Applicant: OMRON TATEISI ELECTRONICS CO

Inventor： ONO KAZUYUKI ,  TANAKA YOSHIO ,  NAKAJIMA KIYOSHI ,  KURATANI NAOTO ,  MAEKAWA TOMOFUMI

IPC: H01L23/04 ,  H01L23/10 ,  H01L23/552 ,  H05K3/34

CPC classification number: H05K3/341 ,  H01L23/055 ,  H01L23/10 ,  H01L23/552 ,  H01L24/48 ,  H01L24/73 ,  H01L2224/05554 ,  H01L2224/32225 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/48235 ,  H01L2224/73265 ,  H01L2924/00014 ,  H01L2924/01004 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/10162 ,  H01L2924/14 ,  H01L2924/1433 ,  H01L2924/16152 ,  H01L2924/16251 ,  H01L2924/16315 ,  H01L2924/1632 ,  H01L2924/3025 ,  H05K3/3452 ,  H05K2201/099 ,  H05K2201/10371 ,  Y02P70/613 ,  H01L2924/00012 ,  H01L2924/00 ,  H01L2224/45099 ,  H01L2224/45015 ,  H01L2924/207

Abstract: A package for storing a semiconductor element mounted on an upper surface of a substrate (52) is configured by a substrate (52) and a conductive cap (54). A grounding electrode (57) is annularly formed on an upper surface outer circumferential section of the substrate (52). An upper surface of an inner circumferential section of the grounding electrode (57) is covered with a solder resist (67). On an outer circumference lower end surface of the conductive cap (54), a flange (70) substantially horizontally bent is formed. The conductive cap (54) is arranged on the upper surface of the substrate (52), and a lower surface of the flange (70) is permitted to abut to an upper surface of the solder resist (67). Furthermore, on a further outer circumferential side from the solder resist (67), a space formed between the lower surface of the flange (70) and the grounding electrode (57) is filled with a conductive bonding member (73), and the conductive cap (54) is bonded to the substrate (52).

Abstract translation: 用于存储安装在基板（52）的上表面上的半导体元件的封装由基板（52）和导电盖（54）构成。 接地电极（57）环形地形成在基板（52）的上表面外周部分上。 接地电极（57）的内周部的上表面被阻焊剂（67）覆盖。 在导电盖（54）的外周下端面上形成大致水平弯曲的凸缘（70）。 导电盖（54）布置在基板（52）的上表面上，并且凸缘（70）的下表面被允许邻接阻焊剂（67）的上表面。 此外，在阻焊剂（67）的另外的外周侧，在凸缘（70）的下表面和接地电极（57）之间形成的空间填充有导电性接合部件（73），导电性 帽（54）结合到基底（52）上。