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公开(公告)号：EP3128535B1
公开(公告)日：2020-06-03
申请号：EP15773856.8
申请日：2015-03-10
申请人： Toyo Tanso Co., Ltd.
IPC分类号： H01L21/302 , H01L21/205 , C30B29/36 , C30B33/08
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2.发明授权
公开(公告)号：EP3128047B1
公开(公告)日：2018-09-26
申请号：EP15773120.9
申请日：2015-03-10
申请人： Toyo Tanso Co., Ltd.
IPC分类号： H01L21/3065 , H01L21/302 , H01L21/324 , H01L21/205 , H01L21/67 , C30B19/04 , C30B19/12 , C30B29/36 , C30B33/12 , H01L21/02 , H01L29/16
CPC分类号： C30B19/12 , C30B19/04 , C30B29/36 , C30B33/12 , H01L21/02019 , H01L21/02378 , H01L21/02529 , H01L21/02658 , H01L21/302 , H01L21/3065 , H01L21/3247 , H01L21/67069 , H01L21/67109 , H01L21/67115 , H01L29/1608
摘要： Provided is a method in which the rate of growth is not lowered even when a cut SiC seed crystal is used in performing MSE process. A SiC seed crystal that is used as a seed crystal in metastable solvent epitaxy process (MSE process) is heated under Si atmosphere and the surface of the SiC seed crystal is etched to remove a work-affected layer that was formed by cutting. Work-affected layers generated on SiC seed crystals are known to inhibit growth during MSE process, and therefore removing the work-affected layers can prevent lowering of the rate of growth.
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公开(公告)号：EP3162913A1
公开(公告)日：2017-05-03
申请号：EP15812047.7
申请日：2015-06-01
申请人： Toyo Tanso Co., Ltd.
IPC分类号： C23C16/04 , C23C16/458 , C23C16/56 , H01L21/205
摘要： Provided are a susceptor that, in forming a thin film on a wafer, can reduce impurities or the like adhering to the wafer and a method for manufacturing the same. A susceptor includes a base material (10) with a recess (11), a tantalum carbide layer (22) formed directly on a bottom surface (11a) and a side surface (11b) of the recess (11), and a silicon carbide layer (20) formed on a surface of the base material (10) except for the recess (11).
摘要翻译： 本发明提供一种在晶圆上形成薄膜时能够减少附着在晶圆上的杂质等的基座及其制造方法。 基座包括具有凹槽（11）的基材（10），直接形成在凹槽（11）的底表面（11a）和侧表面（11b）上的碳化钽层（22），以及碳化硅 形成在除凹部（11）之外的基材（10）的表面上的层（20）。
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4.发明公开
公开(公告)号：EP2657374A1
公开(公告)日：2013-10-30
申请号：EP11850694.8
申请日：2011-06-29
申请人： Toyo Tanso Co., Ltd.
CPC分类号： H01L29/04 , C30B19/00 , C30B19/12 , C30B29/36 , H01L21/02598 , H01L29/1608
摘要： The cost of liquid phase epitaxial growth of a monocrystalline silicon carbide is reduced. A feed material 11 is such that when a surface layer thereof containing a polycrystalline silicon carbide with a 3C crystal polymorph is subjected to X-ray diffraction, a diffraction peak corresponding to a (111) crystal plane and a diffraction peak other than the diffraction peak corresponding to the (111) crystal plane are observed as diffraction peaks corresponding to the polycrystalline silicon carbide with a 3C crystal polymorph. A seed material 12 is such that when a surface layer thereof containing a polycrystalline silicon carbide with a 3C crystal polymorph is subjected to X-ray diffraction, a first-order diffraction peak corresponding to a (111) crystal plane is observed as a diffraction peak corresponding to the polycrystalline silicon carbide with a 3C crystal polymorph but no other first-order diffraction peak having a diffraction intensity of 10% or more of the diffraction intensity of the first-order diffraction peak corresponding to the (111) crystal plane is observed.
摘要翻译： 单晶碳化硅的液相外延生长的成本降低。 的进料材料11被检查并当其含有具有3C晶体多晶型物的多晶碳化硅的表面层进行X射线衍射中，衍射峰对应于（111）晶面和比衍射峰以外的衍射峰 对应于（111）晶面中观察到，如衍射峰对应于多晶碳化硅为3C晶体多晶型物。 种子材料12被检查并当其含有具有3C晶体多晶型物的多晶碳化硅的表面层进行X射线衍射，一阶衍射峰对应于（111）晶面，观察到的衍射峰 对应于多晶碳化硅为3C晶体多晶型物，但是具有的第一阶衍射峰对应于（111）晶面的衍射强度的10％以上的衍射强度没有其它的第一阶衍射峰被观测的。
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公开(公告)号：EP3854916A1
公开(公告)日：2021-07-28
申请号：EP19862939.6
申请日：2019-09-19
申请人： Toyo Tanso Co., Ltd.
IPC分类号： C30B29/36 , C30B33/02 , H01L21/265 , H01L21/324
摘要： In a method for manufacturing a device fabrication wafer 43, an SiC epitaxial wafer 42 that is an SiC wafer 40 having a monocrystalline SiC epitaxial layer 41 formed thereon is subjected to a basal plane dislocation density reduction step of reducing the density of basal plane dislocations existing in the epitaxial layer of the SiC epitaxial wafer 42, to thereby manufacture the device fabrication wafer 43 for use to fabricate a semiconductor device. In the basal plane dislocation density reduction step, the SiC epitaxial wafer 42 is heated under Si vapor pressure for a predetermined time necessary to reduce the density of basal plane dislocations, without formation of a cap layer on the SiC epitaxial wafer 42, so that the density of basal plane dislocations is reduced with suppression of surface roughening.
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公开(公告)号：EP3223303A1
公开(公告)日：2017-09-27
申请号：EP15861337.2
申请日：2015-11-17
发明人： TORIMI, Satoshi , SHINOHARA, Masato , TERAMOTO, Youji , YABUKI, Norihito , NOGAMI, Satoru , KANEKO, Tadaaki , ASHIDA, Koji , KUTSUMA, Yasunori
IPC分类号： H01L21/302 , C30B29/36 , C30B33/12
CPC分类号： H01L21/30604 , C30B29/36 , C30B33/12 , C30B35/002 , H01L21/302 , H01L21/67063
摘要： Provided is a method for controlling the rate of etching of a SiC substrate based on a composition of a storing container. The etching method of the present invention is for etching the SiC substrate by heating the SiC substrate under Si vapor pressure, in a state where the SiC substrate is stored in a crucible. The crucible is formed of a tantalum metal, and has a tantalum carbide layer provided on an internal space side of the tantalum metal, and a tantalum silicide layer provided on the side further toward the internal space side than the tantalum carbide layer. The rate of etching of the SiC substrate is controlled based on difference in a composition of the tantalum silicide layer.
摘要翻译： 提供了一种基于储存容器的组成来控制SiC衬底的蚀刻速率的方法。 本发明的蚀刻方法用于在将SiC基板收纳在坩埚中的状态下，通过在Si蒸气压下加热SiC基板来对SiC基板进行蚀刻。 坩埚由钽金属形成，并且具有设置在钽金属的内部空间侧上的碳化钽层和设置在比碳化钽层更靠近内部空间侧的侧面上的硅化钽层。 基于钽硅化物层的组成差异来控制SiC衬底的蚀刻速率。
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8.发明公开METHOD FOR REMOVING WORK-AFFECTED LAYER ON SiC SEED CRYSTAL, SiC SEED CRYSTAL, AND SiC SUBSTRATE MANUFACTURING METHOD 审中-公开方法用于除去工作损害层上的SiC晶种，SiC晶种和SiC衬底PROCESS
公开(公告)号：EP3128047A1
公开(公告)日：2017-02-08
申请号：EP15773120.9
申请日：2015-03-10
申请人： Toyo Tanso Co., Ltd.
CPC分类号： C30B19/12 , C30B19/04 , C30B29/36 , C30B33/12 , H01L21/02019 , H01L21/02378 , H01L21/02529 , H01L21/02658 , H01L21/302 , H01L21/3065 , H01L21/3247 , H01L21/67069 , H01L21/67109 , H01L21/67115 , H01L29/1608
摘要： Provided is a method in which the rate of growth is not lowered even when a cut SiC seed crystal is used in performing MSE process. A SiC seed crystal that is used as a seed crystal in metastable solvent epitaxy process (MSE process) is heated under Si atmosphere and the surface of the SiC seed crystal is etched to remove a work-affected layer that was formed by cutting. Work-affected layers generated on SiC seed crystals are known to inhibit growth during MSE process, and therefore removing the work-affected layers can prevent lowering of the rate of growth.
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9.发明公开SURFACE TREATMENT METHOD FOR SINGLE CRYSTAL SiC SUBSTRATE, AND SINGLE CRYSTAL SiC SUBSTRATE 审中-公开AT AT AT AT EN EN AT AT AT AT AT AT AT AT AT AT AT AT AT AT AT AT AT AT AT
公开(公告)号：EP2921574A1
公开(公告)日：2015-09-23
申请号：EP13854743.5
申请日：2013-11-15
申请人： Toyo Tanso Co., Ltd.
CPC分类号： H01L21/0445 , C30B29/36 , C30B31/22 , C30B33/02 , C30B33/08 , C30B33/12 , H01L21/3065 , H01L29/1608
摘要： The present application aims to provide a surface treatment method that is able to accurately control the rate of etching a single crystal SiC substrate and thereby enables correct understanding of the amount of etching. In the surface treatment method, the single crystal SiC substrate is etched by a heat treatment performed under Si vapor pressure. At a time of the etching, inert gas pressure in an atmosphere around the single crystal SiC substrate is adjusted to control the rate of etching. Accordingly, correct understanding of the amount of etching is obtained.
摘要翻译： 本申请旨在提供一种表面处理方法，其能够精确地控制蚀刻单晶SiC衬底的速率，从而能够正确地理解蚀刻量。 在表面处理方法中，通过在Si蒸气压下进行的热处理蚀刻单晶SiC衬底。 在蚀刻时，调整单晶SiC衬底周围的气氛中的惰性气体压力，以控制蚀刻速率。 因此，获得对蚀刻量的正确理解。
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公开(公告)号：EP4033519A1
公开(公告)日：2022-07-27
申请号：EP20864989.7
申请日：2020-06-18
发明人： KOBAYASHI, Keisuke , KONISHI. Kumiko , SHIMA, Akio , YABUKI, Norihito , SUDOH, Yusuke , NOGAMI, Satoru , KITABATAKE, Makoto
IPC分类号： H01L21/324 , H01L29/78 , H01L29/12 , H01L21/336
摘要： To provide a technique capable of improving performance and reliability of a semiconductor device. An n - -type epitaxial layer (12) is formed on an n-type semiconductor substrate (11), and a p + -type body region (14), n + -type current spreading regions (16, 17), and a trench TR are formed in the n - -type epitaxial layer (12). A bottom surface B1 of the trench TR is located in the p + -type body region (14), a side surface S1 of the trench TR is in contact with the n + -type current spreading region (17), and a side surface S2 of the trench TR is in contact with the n + -type current spreading region (16). Here, a ratio of silicon is higher than a ratio of carbon in an upper surface T1 of the r - -type epitaxial layer (12), and the bottom surface B1, the side surface S1, and the side surface S2 of the trench. Furthermore, an angle θ1 at which the upper surface T1 of the n - -type epitaxial layer (12) is inclined with respect to the side surface S1 is smaller than an angle θ2 at which the upper surface T1 of the n - -type epitaxial layer (12) is inclined with respect to the side surface S2.
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