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    Method for forming metal circuit, liquid trigger material for forming metal circuit and metal circuit structure
    7.
    发明公开
    Method for forming metal circuit, liquid trigger material for forming metal circuit and metal circuit structure 审中-公开
    一种用于制造金属电路的方法，液体释放材料以形成金属电路和金属电路图案

    公开(公告)号：EP2869309A1

    公开(公告)日：2015-05-06

    申请号：EP14177426.5

    申请日：2014-07-17

    申请人： Industrial Technology Research Institute

    发明人： Kao, Tune-Hune ,  Huang, Meng-Chi ,  Chou, Min-Chieh

    IPC分类号： H01B1/14 ,  H05K1/09 ,  H05K3/18 ,  H05K3/24 ,  H05K3/46

    CPC分类号： C23C18/1651 ,  C09D5/24 ,  C23C18/1608 ,  C23C18/1612 ,  C23C18/165 ,  H05K1/0296 ,  H05K1/0373 ,  H05K3/107 ,  H05K3/185 ,  H05K3/4661 ,  H05K3/4676 ,  H05K2201/0209

    摘要： A metal circuit structure, a method for forming a metal circuit and a liquid trigger material for forming a metal circuit are provided. The metal circuit structure includes a substrate, a first trigger layer and a first metal circuit layer. The first trigger layer is disposed on the substrate and includes a first metal circuit pattern. The first metal circuit layer is disposed on the first circuit pattern and is electrically insulated from the substrate. The composition of the first trigger layer includes an insulating gel and a plurality of trigger particles. The trigger particles are at least one of organometallic particles, a chelation and a semiconductor material having an energy gap greater than or equal to 3 eV. The trigger particles are disposed in the insulating gel, such that the dielectric constant of the first trigger layer after curing is between 2 and 6.5.

    摘要翻译： 本发明提供一种金属的电路结构，用于形成金属电路和用于形成金属电路的液体触发材料的方法。 金属电路结构包括一个基片，一个第一触发层和第一金属层电路。 第一触发层配置在基板上，并且包括第一金属电路图案。 第一金属线路层设置在第一电路图案和电从衬底绝缘。 第一触发层的组合物包括在绝缘凝胶和触发颗粒的复数。 触发颗粒是有机金属颗粒，螯合和具有能隙大于或等于3电子伏特的半导体材料中的至少一种。 所述触发粒子被设置在所述绝缘凝胶，检查做的第一触发层的介电常数后固化是2和6.5之间。

    PRINTED CIRCUIT BOARD AND METHOD OF MANUFACTURING THE SAME
    8.
    发明公开
    PRINTED CIRCUIT BOARD AND METHOD OF MANUFACTURING THE SAME 审中-公开
    印刷电路板及其制造方法

    公开(公告)号：EP2823696A1

    公开(公告)日：2015-01-14

    申请号：EP13757377.0

    申请日：2013-02-25

    申请人： LG Innotek Co., Ltd.

    发明人： KIM, Ji Su ,  CHUN, Ki Do ,  LEE, Kyu Won ,  LEE, Sang Myung

    IPC分类号： H05K3/46 ,  H05K1/18

    CPC分类号： H05K3/4602 ,  H05K1/0306 ,  H05K1/115 ,  H05K1/181 ,  H05K1/185 ,  H05K3/107 ,  H05K3/465 ,  H05K3/4697 ,  H05K2201/017 ,  H05K2201/0195 ,  H05K2201/20

    摘要： Provided is a printed circuit board, including: a core substrate including an internal circuit pattern on an upper surface or a lower surface; electronic devices which are formed to pass through the core substrate; an external insulating layer which covers the internal circuit pattern and the electronic devices; and an external circuit pattern which is formed on an upper surface of the external insulating layer, wherein a lower surface of the electronic devices protrudes from the lower surface of the core substrate to a lower part. Accordingly, in the embedded printed circuit board in which the electronic devices are embedded, when the electronic devices are mounted, because the insulating layer is formed regardless of a thickness of the electronic devices, the printed circuit board having a desired thickness regardless of the thickness of the electronic devices can be formed.

    摘要翻译： 提供了一种印刷电路板，包括：在上表面或下表面上包括内部电路图案的核心基板; 形成为穿过核心基板的电子器件; 覆盖内部电路图案和电子器件的外部绝缘层; 以及形成在外部绝缘层的上表面上的外部电路图案，其中电子器件的下表面从核心基板的下表面突出到下部。 因此，在嵌入有电子器件的嵌入式印刷电路板中，当安装电子器件时，由于形成绝缘层而与电子器件的厚度无关，所以无论厚度如何，都具有期望厚度的印刷电路板 可以形成电子装置。

    SELECTIVE SEED LAYER TREATMENT FOR FEATURE PLATING
    9.
    发明公开
    SELECTIVE SEED LAYER TREATMENT FOR FEATURE PLATING 审中-公开
    选择性KEIM层结构FOR涂覆处理

    公开(公告)号：EP2647266A1

    公开(公告)日：2013-10-09

    申请号：EP11813464.2

    申请日：2011-12-02

    申请人： Qualcomm Incorporated

    发明人： BCHIR, Omar J. ,  SHAH, Milind P. ,  MOVVA, Sashidhar

    IPC分类号： H05K3/10 ,  H05K3/18 ,  C23C18/30

    CPC分类号： H05K3/185 ,  C23C18/1608 ,  C25D5/02 ,  H05K3/107 ,  H05K2203/0709 ,  H05K2203/107

    摘要： Conventional metallization processes fail at high density or small feature size patterns. For example, during patterning dry films may collapse or lift-off resulting in short circuits or open circuits in the metallization pattern. An exemplary method for metallization of integrated circuits includes forming features such as trenches, pads, and planes in a dielectric layer and depositing and selectively treating a seed layer in desired features of the dielectric layer. The treated regions of the seed layer may be used as a seed for electroless deposition of conductive material, such as copper, into the features. When the seed layer is a catalytic ink, the seed layer may be treated by curing the catalytic ink with a laser.