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公开(公告)号：EP3391415A1
公开(公告)日：2018-10-24
申请号：EP15828622.9
申请日：2015-12-30
IPC分类号： H01L27/18 , H01L23/498
CPC分类号： H01L39/045 , H01L23/49816 , H01L23/49888 , H01L24/03 , H01L24/05 , H01L24/10 , H01L24/11 , H01L24/13 , H01L24/16 , H01L24/81 , H01L25/0657 , H01L25/18 , H01L25/50 , H01L27/18 , H01L2224/0345 , H01L2224/0362 , H01L2224/0381 , H01L2224/03826 , H01L2224/0384 , H01L2224/0401 , H01L2224/05023 , H01L2224/05025 , H01L2224/05124 , H01L2224/05179 , H01L2224/05186 , H01L2224/05564 , H01L2224/05568 , H01L2224/05669 , H01L2224/05684 , H01L2224/05686 , H01L2224/1145 , H01L2224/1181 , H01L2224/13023 , H01L2224/13109 , H01L2224/13116 , H01L2224/13164 , H01L2224/13179 , H01L2224/13183 , H01L2224/16145 , H01L2224/81013 , H01L2224/81193 , H01L2224/81201 , H01L2224/81409 , H01L2225/06513 , H01L2225/06541 , H01L2924/10253 , H01L2924/10271 , H01L2924/10329 , H01L2924/20102 , H01L2924/00014 , H01L2924/04941
摘要： A device (100) includes a first chip (104) having a first circuit element (112), a first interconnect pad (116) in electrical contact (118) with the first circuit element, and a barrier layer (120) on the first interconnect pad, a superconducting bump bond (106) on the barrier layer, and a second chip (102) joined to the first chip by the superconducting bump bond, the second chip having a quantum circuit element (108), in which the superconducting bump bond provides an electrical connection between the first circuit element and the quantum circuit element.
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2.发明公开Die with a multilayer backside interface layer for solder bonding to a substrate and corresponding manufacturing method 审中-公开芯片与多层背面用于向基板钎焊连接和相应的生产方法
公开(公告)号：EP2889903A1
公开(公告)日：2015-07-01
申请号：EP13199587.0
申请日：2013-12-24
申请人： NXP B.V.
IPC分类号： H01L23/482 , H01L21/60 , H01L23/66
CPC分类号： H01L24/29 , H01L23/4827 , H01L23/66 , H01L24/03 , H01L24/05 , H01L24/27 , H01L24/32 , H01L24/83 , H01L2223/6644 , H01L2224/03825 , H01L2224/03826 , H01L2224/05026 , H01L2224/0508 , H01L2224/05082 , H01L2224/05083 , H01L2224/05139 , H01L2224/05144 , H01L2224/05155 , H01L2224/05644 , H01L2224/2745 , H01L2224/2746 , H01L2224/27464 , H01L2224/29084 , H01L2224/29111 , H01L2224/29139 , H01L2224/29144 , H01L2224/29147 , H01L2224/29155 , H01L2224/32245 , H01L2224/32502 , H01L2224/83203 , H01L2224/83207 , H01L2224/83444 , H01L2224/83805 , H01L2924/01028 , H01L2924/01047 , H01L2924/01079 , H01L2924/014 , H01L2924/1421 , H01L2924/15747 , H01L2924/00014 , H01L2924/0105 , H01L2924/01014
摘要： A die (1) comprising a body (3) of semiconductor material, said body (3) configured to receive a solder layer (4) of e.g. an alloy of gold and tin for use in die bonding said die (1) to a substrate (2), wherein the die includes an interface layer (5) on a surface of the body (3) for receiving the solder layer (4), the interface layer (5) having a plurality of sub-layers (5a, 5b, 5c, 5d) of different metals. The interface layer (5) preferably comprises a first sub-layer (5a) of gold applied to the body (3), a second sub-layer (5b) of silver, a third sub-layer (5c) of nickel and a fourth sub-layer (5d) of gold adjoining the solder layer (4). The substrate (2) is preferably made of a copper substrate block (6) with a pad (7) of silver thereon, the substrate (6) and the pad (7) being plated with an outer layer (8) comprising sub-layers of nickel, palladium and gold.
摘要翻译： A为（1），包括主体（3）的半导体材料构成，所述主体（3）被配置为接收一个焊料层（4）的E.G. 的金与锡为在接合用基板合金的所述第（1）到（2），worin模具在本体（3）的表面上的界面层（5）包括用于接收所述焊料层（4） 中，具有不同的金属子层（5A，5B，5C，5D）的多个界面层（5）。 界面层（5）优选地包括金施加到主体（3），第二子层的银的（图5b），第三子层的镍和四分之一的（5C）的第一子层（5a）中 的金子层（5d）的相邻钎焊层（4）。 基板（2）优选为（6），在其上的银的垫（7）由铜基板块的，所述底物（6）和所述垫（7）与在外层镀（8）包括子层 镍，钯和金。
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公开(公告)号：EP2416634A1
公开(公告)日：2012-02-08
申请号：EP10171612.4
申请日：2010-08-02
发明人： Matejat, Kai-Jens , Lamprecht, Sven , Ewert, Ingo
CPC分类号： H05K3/3473 , H01L21/4853 , H01L23/49816 , H01L24/03 , H01L24/05 , H01L24/11 , H01L24/13 , H01L24/16 , H01L2224/03825 , H01L2224/03826 , H01L2224/0401 , H01L2224/05611 , H01L2224/05639 , H01L2224/05644 , H01L2224/05647 , H01L2224/05655 , H01L2224/05664 , H01L2224/05666 , H01L2224/05671 , H01L2224/11462 , H01L2224/11474 , H01L2224/1148 , H01L2224/11622 , H01L2224/11825 , H01L2224/11849 , H01L2224/13099 , H01L2224/13111 , H01L2224/13399 , H01L2224/16145 , H01L2224/16225 , H01L2224/16227 , H01L2924/01005 , H01L2924/01006 , H01L2924/01012 , H01L2924/01013 , H01L2924/01019 , H01L2924/01023 , H01L2924/01024 , H01L2924/01029 , H01L2924/0103 , H01L2924/01033 , H01L2924/01044 , H01L2924/01045 , H01L2924/01047 , H01L2924/01049 , H01L2924/01051 , H01L2924/01052 , H01L2924/01061 , H01L2924/01077 , H01L2924/01078 , H01L2924/01079 , H01L2924/01082 , H01L2924/014 , H01L2924/10253 , H01L2924/12042 , H01L2924/14 , H01L2924/15311 , H01L2924/15787 , H01L2924/351 , H05K3/4007 , H05K2201/0367 , H05K2203/054 , H05K2203/0577 , H01L2924/00
摘要： Described is a method of forming a solder deposit on a substrate comprising the following steps i) provide a substrate (102) including a permanent resin layer (103) on top of at least one contact area (101) and a temporary resin layer (104) on top of the permanent resin layer (103), ii) contact the entire substrate area including the at least one contact area (101) with a solution suitable to provide a conductive layer (106) on the substrate surface, iii) electroplate a solder deposit layer (107) containing tin or a tin alloy onto the conductive layer (106) and iv) etch away an amount of the solder deposit layer (107) containing tin or a tin alloy sufficient to remove the solder deposit layer (107) from the temporary resin layer (104) area leaving a solder material layer (107) on the at least one contact area (101).
摘要翻译： 描述了一种在基板上形成焊料沉积物的方法，包括以下步骤：i）提供在至少一个接触区域（101）和临时树脂层（104）之上包括永久树脂层（103）的基板（102） ）在所述永久性树脂层（103）的顶部上，ii）使包括所述至少一个接触区域（101）的整个基板区域与适合于在所述基板表面上提供导电层（106）的溶液接触，iii）电镀 包含锡或锡合金的焊料沉积层（107）到所述导电层（106）上并且iv）蚀刻掉足以移除所述焊料沉积层（107）的含锡或锡合金的所述焊料沉积层（107） 从所述临时树脂层（104）区域在所述至少一个接触区域（101）上留下焊料材料层（107）。
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