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公开(公告)号：EP2543064A1
公开(公告)日：2013-01-09
申请号：EP10774342.9
申请日：2010-10-15
申请人： Xilinx, Inc.
发明人： RAHMAN, Arifur , MURALI, Venkatesan
IPC分类号： H01L21/98 , H01L25/065 , H01L23/538 , H01L23/00 , H01L21/68 , H01L23/31 , H01L21/56
CPC分类号： H01L21/82 , H01L21/561 , H01L21/568 , H01L21/6835 , H01L23/3114 , H01L23/5389 , H01L24/13 , H01L24/19 , H01L24/20 , H01L24/24 , H01L24/80 , H01L24/82 , H01L24/83 , H01L24/96 , H01L25/0655 , H01L25/16 , H01L25/50 , H01L2221/6834 , H01L2221/68359 , H01L2224/0401 , H01L2224/04105 , H01L2224/08137 , H01L2224/12105 , H01L2224/24101 , H01L2224/24137 , H01L2224/24226 , H01L2224/2902 , H01L2224/29187 , H01L2224/30181 , H01L2224/30183 , H01L2224/32137 , H01L2224/73267 , H01L2224/80006 , H01L2224/80896 , H01L2224/83005 , H01L2224/83896 , H01L2224/92244 , H01L2224/96 , H01L2224/97 , H01L2924/01027 , H01L2924/01033 , H01L2924/014 , H01L2924/10253 , H01L2924/10271 , H01L2924/14 , H01L2924/141 , H01L2924/1431 , H01L2924/1433 , H01L2924/14335 , H01L2924/1434 , H01L2924/1437 , H01L2924/1438 , H01L2924/1443 , H01L2924/145 , H01L2924/15311 , H01L2924/181 , H01L2224/11 , H01L2224/19 , H01L2224/82 , H01L2924/00 , H01L2224/83
摘要： An integrated circuit (IC) combines a first IC chip (die) having a first on-chip interconnect structure and a second IC chip having a second on-chip interconnect structure on a reconstructed wafer base. The second IC chip is edge-bonded to the first IC chip with oxide-to-oxide edge bonding. A chip-to-chip interconnect structure electrically couples the first IC chip and the second IC chip.
摘要翻译： 集成电路（IC）将具有第一片上互连结构的第一IC芯片（芯片）和具有第二片上互连结构的第二IC芯片组合在重建的晶片基座上。 第二IC芯片与氧化物到氧化物边缘接合边缘接合到第一IC芯片。 芯片到芯片的互连结构电耦合第一IC芯片和第二IC芯片。
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公开(公告)号：EP1360723A2
公开(公告)日：2003-11-12
申请号：EP02709238.6
申请日：2002-02-01
发明人： FORBES, Leonard , AHN, Kie, Y.
IPC分类号： H01L23/538 , H01L21/48 , H01L23/48
CPC分类号： H05K1/0222 , H01L21/76898 , H01L23/147 , H01L23/3128 , H01L23/481 , H01L23/49827 , H01L2223/6622 , H01L2924/0002 , H01L2924/10252 , H01L2924/10253 , H01L2924/10271 , H01L2924/10329 , H01L2924/14 , H01L2924/1432 , H01L2924/1435 , H01L2924/145 , H01L2924/15311 , H01L2924/157 , H05K1/115 , H05K2201/09036 , H05K2201/09809 , H05K2201/09845 , H01L2924/00
摘要： The present invention provides a semiconductive substrate (12) which includes front (14) and back surfaces (16) and a hole (18, 20, 22) which extends through the substrate and between the front (14) and back surfaces (16). The hole (18, 20, 22) is defined in part by an interior wall portion and forms an outer conductive sheath. Conductive material (54) is formed proximate at least some of the interior wall portion. Subsequently, a layer of dielectric material (56) is formed within the hole, over and radially inwardly of the conductive material. A second conductive material (60) is then formed within the hole over and radially inwardly of the dielectric material layer (56). The latter conductive material constitutes an inner conductive coaxial line component.
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公开(公告)号：EP1407491A2
公开(公告)日：2004-04-14
申请号：EP02704441.1
申请日：2002-02-22
发明人： BAZARJANI, Seyfollah , ZHANG, Haitao , ZOU, Quizhen , JHA, Sanjay
IPC分类号： H01L25/18 , H01L25/065
CPC分类号： H01L25/0657 , G01R31/2853 , H01L23/3128 , H01L24/48 , H01L24/49 , H01L24/73 , H01L25/18 , H01L2224/05554 , H01L2224/05599 , H01L2224/06164 , H01L2224/06165 , H01L2224/32145 , H01L2224/32225 , H01L2224/45099 , H01L2224/48145 , H01L2224/48227 , H01L2224/49171 , H01L2224/49175 , H01L2224/73265 , H01L2224/85399 , H01L2225/06506 , H01L2225/0651 , H01L2225/06582 , H01L2924/00014 , H01L2924/14 , H01L2924/141 , H01L2924/143 , H01L2924/1435 , H01L2924/145 , H01L2924/15311 , H01L2924/19041 , H01L2924/00 , H01L2924/00012 , H01L2224/45015 , H01L2924/207
摘要： Techniques for fabricating analog and digital circuits on separate dies and stacking and integrating the dies within a single package to form a mixed-signal IC that provides many benefits. In one aspect, the analog and digital circuits are implemented on two separate dies using possibly different IC processes suitable for these different types of circuits. The analog and digital dies are thereafter integrated (stacked) and encapsulated within the single package. Bonding pads are provided to interconnect the dies and to connect the dies to external pins. The bonding pads maybe located and arranged in a manner to provide the required connectivity while minimizing the amount of die area required to implement the pads. In another aspect, the die-to-die connectivity may be tested in conjunction with a serial bus interface. are provided to interconnect the
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公开(公告)号：EP2543064B1
公开(公告)日：2018-08-01
申请号：EP10774342.9
申请日：2010-10-15
申请人： Xilinx, Inc.
发明人： RAHMAN, Arifur , MURALI, Venkatesan
IPC分类号： H01L25/065 , H01L21/98 , H01L21/60 , H01L23/538 , H01L23/31 , H01L21/56
CPC分类号： H01L21/82 , H01L21/561 , H01L21/568 , H01L21/6835 , H01L23/3114 , H01L23/5389 , H01L24/13 , H01L24/19 , H01L24/20 , H01L24/24 , H01L24/80 , H01L24/82 , H01L24/83 , H01L24/96 , H01L25/0655 , H01L25/16 , H01L25/50 , H01L2221/6834 , H01L2221/68359 , H01L2224/0401 , H01L2224/04105 , H01L2224/08137 , H01L2224/12105 , H01L2224/24101 , H01L2224/24137 , H01L2224/24226 , H01L2224/2902 , H01L2224/29187 , H01L2224/30181 , H01L2224/30183 , H01L2224/32137 , H01L2224/73267 , H01L2224/80006 , H01L2224/80896 , H01L2224/83005 , H01L2224/83896 , H01L2224/92244 , H01L2224/96 , H01L2224/97 , H01L2924/01027 , H01L2924/01033 , H01L2924/014 , H01L2924/10253 , H01L2924/10271 , H01L2924/14 , H01L2924/141 , H01L2924/1431 , H01L2924/1433 , H01L2924/14335 , H01L2924/1434 , H01L2924/1437 , H01L2924/1438 , H01L2924/1443 , H01L2924/145 , H01L2924/15311 , H01L2924/181 , H01L2224/11 , H01L2224/19 , H01L2224/82 , H01L2924/00 , H01L2224/83
摘要： An integrated circuit (IC) combines a first IC chip (die) having a first on-chip interconnect structure and a second IC chip having a second on-chip interconnect structure on a reconstructed wafer base. The second IC chip is edge-bonded to the first IC chip with oxide-to-oxide edge bonding. A chip-to-chip interconnect structure electrically couples the first IC chip and the second IC chip.
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