公开(公告)号：EP3385983A1

公开(公告)日：2018-10-10

申请号：EP17164700.1

申请日：2017-04-04

申请人： Heraeus Deutschland GmbH & Co. KG

发明人： KLEIN, Andreas ,  HINRICH, Andreas ,  DIETRICH, Peter

IPC分类号： H01L23/485 ,  H01L23/49 ,  H01L21/60 ,  H01L21/603 ,  H01L21/683

CPC分类号： H01L24/05 ,  H01L21/6835 ,  H01L24/06 ,  H01L24/40 ,  H01L24/48 ,  H01L2221/68331 ,  H01L2224/03334 ,  H01L2224/03505 ,  H01L2224/0401 ,  H01L2224/04026 ,  H01L2224/04034 ,  H01L2224/04042 ,  H01L2224/05553 ,  H01L2224/05557 ,  H01L2224/0556 ,  H01L2224/05573 ,  H01L2224/05582 ,  H01L2224/05639 ,  H01L2224/05644 ,  H01L2224/05655 ,  H01L2224/05664 ,  H01L2224/06051 ,  H01L2224/06165 ,  H01L2224/4013 ,  H01L2224/40491 ,  H01L2224/48491 ,  H01L2924/00014 ,  H01L2224/05155 ,  H01L2224/05164 ,  H01L2924/00012

摘要： Ein Adaptersystem zur Kontaktbereichsvergrößerung zumindest einer Kontaktoberfläche (11, 11a', 11b', 11c', 11d', 11e', 11f', 11") auf zumindest einem Elektronikbauteil (9, 9', 9") (z.B. einem Leistungshalbleiter) weist auf: zumindest ein Substrat (3, 3a', 3b', 3") mit einer ersten Seite und einer der ersten Seite gegenüberliegenden zweiten Seite; und zumindest ein Kontaktierungselement (5, 5a', 5"), das zumindest bereichsweise auf der ersten Seite des Substrats (3, 3a', 3b', 3") angeordnet ist, wobei das Kontaktierungselement (5, 5a', 5") angepasst ist, die erste Seite mit der Kontaktoberfläche (11, 11a', 11b', 11c', 11d', 11e', 11f', 11") des Elektronikbauteils (9, 9', 9") elektrisch zu verbinden, wobei eine Oberfläche der zweiten Seite des Substrats (3, 3a', 3b', 3") größer ist als die Kontaktoberfläche (11, 11a', 11b', 11c', 11d', 11e', 11") des Elektronikbauteils (9, 9', 9"). Das Adaptersystem kann weiter zumindest ein Fixierungselement (7, 7a', 7") aufweisen, das auf der ersten Seite des Substrats (3, 3a', 3b', 3") zumindest bereichsweise um das Kontaktierungselement (5, 5a', 5") herum angeordnet ist, wobei das Fixierungselement (7, 7a', 7") angepasst ist das Elektronikbauteil (9, 9', 9") mechanisch zu kontaktieren, insbesondere die erste Seite des Substrats (3, 3a', 3b', 3") mit dem Elektronikbauteil (9, 9', 9") mechanisch zu verbinden. Die zweite Seite des Substrats (3, 3a', 3b', 3") kann zum Verbinden mit einem Verbindungselement, insbesondere mit einem Bonddraht, angepasst sein. Das Substrat (3, 3a', 3b', 3") kann ein elektrisch leitendes Material aufweisen. Das Kontaktierungselement (5, 5a', 5") kann eine Sinterpaste aufweisen. Es können zumindest zwei Substrate (3a', 3b') zumindest bereichsweise auf dem Elektronikbauteil (9') angeordnet sein und/oder mindestens zwei Kontaktoberflächen (11b', 11c', 11d', 11e', 11f') mit einem einzelnen Kontaktierungselement (5, 5a', 5") elektrisch verbunden sein.

公开(公告)号：EP2775527A2

公开(公告)日：2014-09-10

申请号：EP13190751.1

申请日：2013-10-29

申请人： Kabushiki Kaisha Toshiba

发明人： Takagi, Kazutaka

IPC分类号： H01L29/417 ,  H01L29/778 ,  H01L23/64 ,  H01L29/20

CPC分类号： H01L29/0696 ,  H01L23/66 ,  H01L24/06 ,  H01L24/48 ,  H01L24/49 ,  H01L29/2003 ,  H01L29/41758 ,  H01L29/7786 ,  H01L2223/6611 ,  H01L2223/6655 ,  H01L2224/04042 ,  H01L2224/06165 ,  H01L2224/48227 ,  H01L2224/49175 ,  H01L2924/00014 ,  H01L2924/10272 ,  H01L2924/1033 ,  H01L2924/12032 ,  H01L2924/1306 ,  H01L2924/13064 ,  H01L2924/19107 ,  H01L2924/30107 ,  H01L2924/00 ,  H01L2224/45099 ,  H01L2224/45015 ,  H01L2924/207

摘要： A field effect transistor has a plurality of cells (52) provided on a first straight line (90). Each cell has a plurality of multi-finger electrodes and is connected to a gate terminal electrode (33) and a drain terminal electrode (53). The multi-finger electrode has at least two finger gate electrodes, a finger drain electrode, and a finger source electrode. The gate terminal electrode connects the finger gate electrodes of two adjoining cells in common. The drain terminal electrode connects the finger drain electrodes of two adjoining cells in common. The finger gate electrode of one cell of two adjoining cells and the finger gate electrode of another cell of the two adjoining cells cross perpendicularly. The gate terminal electrode and the drain terminal electrode are provided alternately in a region where the finger gate electrodes of the two adjoining cells cross.

摘要翻译： 场效应晶体管具有设置在第一直线（90）上的多个单元（52）。 每个单元具有多个多指电极，并连接到栅极端子电极（33）和漏极端子电极（53）。 多指电极具有至少两个指状栅电极，指状漏电极和指状电极。 栅极端子电极共同连接两个邻接的电池的手指栅电极。 漏极端子电极共同连接两个相邻单元的指状漏电极。 两个相邻单元的一个单元的指状栅极和两个相邻单元的另一个单元的指状栅电极垂直交叉。 栅极端子电极和漏极端子电极交替设置在两个相邻单元的指状栅电极交叉的区域。

公开(公告)号：EP1253640A3

公开(公告)日：2004-03-03

申请号：EP02252687.5

申请日：2002-04-16

申请人： Tyco Electronics Corporation

发明人： Palmteer, William James ,  Beucler, Philip Joseph

IPC分类号： H01L23/495

CPC分类号： H01L24/06 ,  H01L23/49503 ,  H01L23/49575 ,  H01L24/48 ,  H01L24/49 ,  H01L2224/05554 ,  H01L2224/05599 ,  H01L2224/0603 ,  H01L2224/06165 ,  H01L2224/32245 ,  H01L2224/48091 ,  H01L2224/48137 ,  H01L2224/48247 ,  H01L2224/48257 ,  H01L2224/49111 ,  H01L2224/49113 ,  H01L2224/73265 ,  H01L2224/85399 ,  H01L2924/00014 ,  H01L2924/01023 ,  H01L2924/01042 ,  H01L2924/10161 ,  H01L2924/181 ,  H01L2224/45099 ,  H01L2924/00 ,  H01L2924/00012

摘要： A leadframe-based CSP (50) comprises a leadframe (51) having a die attach pad (52) and a plurality of wire bonding pads (54), an aperture (65) disposed in the die attach pad (52), die (56) on the die attach pad, bonding wire(s) (58) electrically interconnecting the dies and the wire bonding pads, and a mold compound (60) which encapsulates the dies and the bonding wires to form the chip package (50) and which is formed in the aperture.

摘要翻译： 基于引线框的CSP（50）包括具有管芯附接焊盘（52）和多个引线接合焊盘（54）的引线框架（51），设置在管芯附接焊盘（52）中的孔（65），管芯 （60），封装模具和接合线以形成芯片封装（50）的模具化合物（60），以及形成芯片封装（50）的模具化合物（60），以及 其形成在孔中。

公开(公告)号：EP1253640A2

公开(公告)日：2002-10-30

申请号：EP02252687.5

申请日：2002-04-16

申请人： Tyco Electronics Corporation

发明人： Palmteer, William James ,  Beucler, Philip Joseph

IPC分类号： H01L23/495

CPC分类号： H01L24/06 ,  H01L23/49503 ,  H01L23/49575 ,  H01L24/48 ,  H01L24/49 ,  H01L2224/05554 ,  H01L2224/05599 ,  H01L2224/0603 ,  H01L2224/06165 ,  H01L2224/32245 ,  H01L2224/48091 ,  H01L2224/48137 ,  H01L2224/48247 ,  H01L2224/48257 ,  H01L2224/49111 ,  H01L2224/49113 ,  H01L2224/73265 ,  H01L2224/85399 ,  H01L2924/00014 ,  H01L2924/01023 ,  H01L2924/01042 ,  H01L2924/10161 ,  H01L2924/181 ,  H01L2224/45099 ,  H01L2924/00 ,  H01L2924/00012

摘要： A leadframe-based CSP (50) comprises a leadframe (51) having a die attach pad (52) and a plurality of wire bonding pads (54), an aperture (65) disposed in the die attach pad (52), die (56) on the die attach pad, bonding wire(s) (58) electrically interconnecting the dies and the wire bonding pads, and a mold compound (60) which encapsulates the dies and the bonding wires to form the chip package (50) and which is formed in the aperture.

摘要翻译： 基于引线框的CSP（50）包括具有管芯附接焊盘（52）和多个引线接合焊盘（54）的引线框架（51），设置在管芯附接焊盘（52）中的孔（65），管芯 （60），封装模具和接合线以形成芯片封装（50）的模具化合物（60），以及形成芯片封装（50）的模具化合物（60），以及 其形成在孔中。

公开(公告)号：EP2764545B1

公开(公告)日：2018-07-04

申请号：EP12775582.5

申请日：2012-10-02

申请人： Invensas Corporation

发明人： CRISP, Richard, Dewitt ,  ZOHNI, Wael ,  HABA, Belgacem ,  LAMBRECHT, Frank

IPC分类号： H01L25/065 ,  H01L23/13 ,  G11C5/02 ,  G11C5/04 ,  G11C5/06

CPC分类号： G11C5/04 ,  G11C5/02 ,  G11C5/063 ,  G11C5/066 ,  H01L23/13 ,  H01L23/3128 ,  H01L23/36 ,  H01L23/49816 ,  H01L23/49827 ,  H01L23/49838 ,  H01L23/50 ,  H01L24/06 ,  H01L24/13 ,  H01L24/16 ,  H01L24/24 ,  H01L24/48 ,  H01L24/49 ,  H01L24/73 ,  H01L25/0652 ,  H01L25/0655 ,  H01L25/0657 ,  H01L25/18 ,  H01L2224/02375 ,  H01L2224/02379 ,  H01L2224/0401 ,  H01L2224/04042 ,  H01L2224/05554 ,  H01L2224/05569 ,  H01L2224/0557 ,  H01L2224/06155 ,  H01L2224/06156 ,  H01L2224/06165 ,  H01L2224/06179 ,  H01L2224/06181 ,  H01L2224/06515 ,  H01L2224/12105 ,  H01L2224/131 ,  H01L2224/13109 ,  H01L2224/13111 ,  H01L2224/13144 ,  H01L2224/13147 ,  H01L2224/16146 ,  H01L2224/16225 ,  H01L2224/16227 ,  H01L2224/24145 ,  H01L2224/32145 ,  H01L2224/32225 ,  H01L2224/48091 ,  H01L2224/48145 ,  H01L2224/48227 ,  H01L2224/4824 ,  H01L2224/48471 ,  H01L2224/49113 ,  H01L2224/49175 ,  H01L2224/73204 ,  H01L2224/73207 ,  H01L2224/73215 ,  H01L2224/73253 ,  H01L2224/73265 ,  H01L2225/06506 ,  H01L2225/06513 ,  H01L2225/06517 ,  H01L2225/06524 ,  H01L2225/06541 ,  H01L2225/06551 ,  H01L2225/06558 ,  H01L2225/06562 ,  H01L2225/06565 ,  H01L2225/06568 ,  H01L2225/06575 ,  H01L2225/06589 ,  H01L2924/00014 ,  H01L2924/01322 ,  H01L2924/10161 ,  H01L2924/1434 ,  H01L2924/1435 ,  H01L2924/1436 ,  H01L2924/1438 ,  H01L2924/15172 ,  H01L2924/15192 ,  H01L2924/15311 ,  H01L2924/157 ,  H01L2924/15787 ,  H01L2924/15788 ,  H01L2924/1579 ,  H01L2924/181 ,  H01L2924/18161 ,  H01L2924/3011 ,  H05K1/181 ,  H05K2201/09227 ,  H05K2201/10159 ,  H01L2924/00012 ,  H01L2924/00 ,  H01L2224/45099 ,  H01L2224/05599

摘要： A microelectronic package (100) can include a plurality of vertically stacked semiconductor chips 632, 637, the front face of at least one chip facing away from a first substrate surface (108), one or more columns (138, 143) of contacts (132) extending in a first direction (142) along surface (108). Columns (104A, 107B, 109A, 109B) of terminals (105 107) exposed at a second substrate surface (110) extend in the first direction. First terminals (105) disposed in a central region (112) of surface (110) which has width (152) not more than three and one-half times a minimum pitch (150) of the columns of terminals can be configured to carry address information usable to determine an addressable memory location. An axial plane of the at least one semiconductor chip can intersect the central region.

公开(公告)号：EP1407491A2

公开(公告)日：2004-04-14

申请号：EP02704441.1

申请日：2002-02-22

申请人： QUALCOMM INCORPORATED

发明人： BAZARJANI, Seyfollah ,  ZHANG, Haitao ,  ZOU, Quizhen ,  JHA, Sanjay

IPC分类号： H01L25/18 ,  H01L25/065

CPC分类号： H01L25/0657 ,  G01R31/2853 ,  H01L23/3128 ,  H01L24/48 ,  H01L24/49 ,  H01L24/73 ,  H01L25/18 ,  H01L2224/05554 ,  H01L2224/05599 ,  H01L2224/06164 ,  H01L2224/06165 ,  H01L2224/32145 ,  H01L2224/32225 ,  H01L2224/45099 ,  H01L2224/48145 ,  H01L2224/48227 ,  H01L2224/49171 ,  H01L2224/49175 ,  H01L2224/73265 ,  H01L2224/85399 ,  H01L2225/06506 ,  H01L2225/0651 ,  H01L2225/06582 ,  H01L2924/00014 ,  H01L2924/14 ,  H01L2924/141 ,  H01L2924/143 ,  H01L2924/1435 ,  H01L2924/145 ,  H01L2924/15311 ,  H01L2924/19041 ,  H01L2924/00 ,  H01L2924/00012 ,  H01L2224/45015 ,  H01L2924/207

摘要： Techniques for fabricating analog and digital circuits on separate dies and stacking and integrating the dies within a single package to form a mixed-signal IC that provides many benefits. In one aspect, the analog and digital circuits are implemented on two separate dies using possibly different IC processes suitable for these different types of circuits. The analog and digital dies are thereafter integrated (stacked) and encapsulated within the single package. Bonding pads are provided to interconnect the dies and to connect the dies to external pins. The bonding pads maybe located and arranged in a manner to provide the required connectivity while minimizing the amount of die area required to implement the pads. In another aspect, the die-to-die connectivity may be tested in conjunction with a serial bus interface. are provided to interconnect the

公开(公告)号：EP2769409A1

公开(公告)日：2014-08-27

申请号：EP12794789.3

申请日：2012-10-03

申请人： Invensas Corporation

发明人： CRISP, Richard, Dewitt ,  ZOHNI, Wael ,  HABA, Belgacem ,  LAMBRECHT, Frank

IPC分类号： H01L25/065 ,  H01L23/498 ,  H01L25/10

CPC分类号： G11C5/02 ,  G11C5/04 ,  G11C5/06 ,  G11C5/063 ,  G11C8/06 ,  G11C8/10 ,  G11C8/18 ,  H01L23/13 ,  H01L23/3128 ,  H01L23/36 ,  H01L23/49816 ,  H01L23/49827 ,  H01L24/16 ,  H01L24/24 ,  H01L24/48 ,  H01L24/49 ,  H01L24/73 ,  H01L24/92 ,  H01L25/0652 ,  H01L25/0655 ,  H01L25/0657 ,  H01L25/105 ,  H01L25/18 ,  H01L2224/02375 ,  H01L2224/02379 ,  H01L2224/0401 ,  H01L2224/04042 ,  H01L2224/05554 ,  H01L2224/06135 ,  H01L2224/06165 ,  H01L2224/16145 ,  H01L2224/16225 ,  H01L2224/16227 ,  H01L2224/24145 ,  H01L2224/32145 ,  H01L2224/32225 ,  H01L2224/45014 ,  H01L2224/48145 ,  H01L2224/48227 ,  H01L2224/4824 ,  H01L2224/49175 ,  H01L2224/73204 ,  H01L2224/73207 ,  H01L2224/73215 ,  H01L2224/73265 ,  H01L2224/9202 ,  H01L2225/06506 ,  H01L2225/0651 ,  H01L2225/06513 ,  H01L2225/06517 ,  H01L2225/06524 ,  H01L2225/06541 ,  H01L2225/06551 ,  H01L2225/06558 ,  H01L2225/06562 ,  H01L2225/06589 ,  H01L2225/1023 ,  H01L2225/1058 ,  H01L2225/107 ,  H01L2924/00014 ,  H01L2924/01029 ,  H01L2924/01322 ,  H01L2924/1431 ,  H01L2924/1434 ,  H01L2924/1436 ,  H01L2924/1438 ,  H01L2924/1443 ,  H01L2924/15311 ,  H01L2924/15321 ,  H01L2924/15331 ,  H01L2924/157 ,  H01L2924/15787 ,  H01L2924/15788 ,  H01L2924/1579 ,  H01L2924/181 ,  H01L2924/18161 ,  H01L2924/19041 ,  H01L2924/19105 ,  H01L2924/3011 ,  H01L2924/00012 ,  H01L2924/00 ,  H01L2224/45099 ,  H01L2224/45015 ,  H01L2924/207

摘要： A microelectronic structure (100) has active elements (202) defining a memory storage array (204), and address inputs (206) for receipt of address information specifying locations within the storage array. The structure has a first surface (201) and can have terminals (104, 106) exposed at the first surface. The terminals may include first terminals (104) and the structure may be configured to transfer address information received at the first terminals to the address inputs. Each first terminal can have a signal assignment which includes one or more of the address inputs. The first terminals are disposed on first and second opposite sides of a theoretical plane (132) normal to the first surface, wherein the signal assignments of the first terminals disposed on the first side are a mirror image of the signal assignments of the first terminals disposed on the second side of the theoretical plane.

摘要翻译： 微电子结构具有定义存储阵列的活动元件，以及用于接收指定存储阵列内的位置的地址信息的地址输入。 该结构具有第一表面并且可以具有在第一表面处露出的端子。 终端可以包括第一终端，并且该结构可以被配置为将在第一终端接收的地址信息传送到地址输入。 每个第一终端可以具有包括一个或多个地址输入的信号分配。 第一端子设置在与第一表面垂直的理论平面的第一和第二相对侧上，其中设置在第一侧上的第一端子的信号分配是设置在第二端上的第一端子的信号分配的镜像 一侧的理论飞机。

公开(公告)号：EP2764545A1

公开(公告)日：2014-08-13

申请号：EP12775582.5

申请日：2012-10-02

申请人： Invensas Corporation

发明人： CRISP, Richard, Dewitt ,  ZOHNI, Wael ,  HABA, Belgacem ,  LAMBRECHT, Frank

IPC分类号： H01L25/065 ,  H01L23/13 ,  G11C5/02 ,  G11C5/04 ,  G11C5/06

CPC分类号： G11C5/04 ,  G11C5/02 ,  G11C5/063 ,  G11C5/066 ,  H01L23/13 ,  H01L23/3128 ,  H01L23/36 ,  H01L23/49816 ,  H01L23/49827 ,  H01L23/49838 ,  H01L23/50 ,  H01L24/06 ,  H01L24/13 ,  H01L24/16 ,  H01L24/24 ,  H01L24/48 ,  H01L24/49 ,  H01L24/73 ,  H01L25/0652 ,  H01L25/0655 ,  H01L25/0657 ,  H01L25/18 ,  H01L2224/02375 ,  H01L2224/02379 ,  H01L2224/0401 ,  H01L2224/04042 ,  H01L2224/05554 ,  H01L2224/05569 ,  H01L2224/0557 ,  H01L2224/06155 ,  H01L2224/06156 ,  H01L2224/06165 ,  H01L2224/06179 ,  H01L2224/06181 ,  H01L2224/06515 ,  H01L2224/12105 ,  H01L2224/131 ,  H01L2224/13109 ,  H01L2224/13111 ,  H01L2224/13144 ,  H01L2224/13147 ,  H01L2224/16146 ,  H01L2224/16225 ,  H01L2224/16227 ,  H01L2224/24145 ,  H01L2224/32145 ,  H01L2224/32225 ,  H01L2224/48091 ,  H01L2224/48145 ,  H01L2224/48227 ,  H01L2224/4824 ,  H01L2224/48471 ,  H01L2224/49113 ,  H01L2224/49175 ,  H01L2224/73204 ,  H01L2224/73207 ,  H01L2224/73215 ,  H01L2224/73253 ,  H01L2224/73265 ,  H01L2225/06506 ,  H01L2225/06513 ,  H01L2225/06517 ,  H01L2225/06524 ,  H01L2225/06541 ,  H01L2225/06551 ,  H01L2225/06558 ,  H01L2225/06562 ,  H01L2225/06565 ,  H01L2225/06568 ,  H01L2225/06575 ,  H01L2225/06589 ,  H01L2924/00014 ,  H01L2924/01322 ,  H01L2924/10161 ,  H01L2924/1434 ,  H01L2924/1435 ,  H01L2924/1436 ,  H01L2924/1438 ,  H01L2924/15172 ,  H01L2924/15192 ,  H01L2924/15311 ,  H01L2924/157 ,  H01L2924/15787 ,  H01L2924/15788 ,  H01L2924/1579 ,  H01L2924/181 ,  H01L2924/18161 ,  H01L2924/3011 ,  H05K1/181 ,  H05K2201/09227 ,  H05K2201/10159 ,  H01L2924/00012 ,  H01L2924/00 ,  H01L2224/45099 ,  H01L2224/05599

摘要： A microelectronic package (100) can include a plurality of vertically stacked semiconductor chips 632, 637, the front face of at least one chip facing away from a first substrate surface (108), one or more columns (138, 143) of contacts (132) extending in a first direction (142) along surface (108). Columns (104A, 107B, 109A, 109B) of terminals (105 107) exposed at a second substrate surface (110) extend in the first direction. First terminals (105) disposed in a central region (112) of surface (110) which has width (152) not more than three and one-half times a minimum pitch (150) of the columns of terminals can be configured to carry address information usable to determine an addressable memory location. An axial plane of the at least one semiconductor chip can intersect the central region.

公开(公告)号：EP1253640B1

公开(公告)日：2007-12-19

申请号：EP02252687.5

申请日：2002-04-16

申请人： TYCO Electronics Corporation

发明人： Palmteer, William James ,  Beucler, Philip Joseph

IPC分类号： H01L23/495 ,  H01L23/66

CPC分类号： H01L24/06 ,  H01L23/49503 ,  H01L23/49575 ,  H01L24/48 ,  H01L24/49 ,  H01L2224/05554 ,  H01L2224/05599 ,  H01L2224/0603 ,  H01L2224/06165 ,  H01L2224/32245 ,  H01L2224/48091 ,  H01L2224/48137 ,  H01L2224/48247 ,  H01L2224/48257 ,  H01L2224/49111 ,  H01L2224/49113 ,  H01L2224/73265 ,  H01L2224/85399 ,  H01L2924/00014 ,  H01L2924/01023 ,  H01L2924/01042 ,  H01L2924/10161 ,  H01L2924/181 ,  H01L2224/45099 ,  H01L2924/00 ,  H01L2924/00012

公开(公告)号：EP2775527A3

公开(公告)日：2016-10-05

申请号：EP13190751.1

申请日：2013-10-29

申请人： Kabushiki Kaisha Toshiba

发明人： Takagi, Kazutaka

IPC分类号： H01L29/778 ,  H01L29/417 ,  H01L29/20 ,  H01L23/66

CPC分类号： H01L29/0696 ,  H01L23/66 ,  H01L24/06 ,  H01L24/48 ,  H01L24/49 ,  H01L29/2003 ,  H01L29/41758 ,  H01L29/7786 ,  H01L2223/6611 ,  H01L2223/6655 ,  H01L2224/04042 ,  H01L2224/06165 ,  H01L2224/48227 ,  H01L2224/49175 ,  H01L2924/00014 ,  H01L2924/10272 ,  H01L2924/1033 ,  H01L2924/12032 ,  H01L2924/1306 ,  H01L2924/13064 ,  H01L2924/19107 ,  H01L2924/30107 ,  H01L2924/00 ,  H01L2224/45099 ,  H01L2224/45015 ,  H01L2924/207

摘要： A field effect transistor has a plurality of cells (52) provided on a first straight line (90). Each cell has a plurality of multi-finger electrodes and is connected to a gate terminal electrode (33) and a drain terminal electrode (53). The multi-finger electrode has at least two finger gate electrodes, a finger drain electrode, and a finger source electrode. The gate terminal electrode connects the finger gate electrodes of two adjoining cells in common. The drain terminal electrode connects the finger drain electrodes of two adjoining cells in common. The finger gate electrode of one cell of two adjoining cells and the finger gate electrode of another cell of the two adjoining cells cross perpendicularly. The gate terminal electrode and the drain terminal electrode are provided alternately in a region where the finger gate electrodes of the two adjoining cells cross.