公开(公告)号：EP1906715A3

公开(公告)日：2014-01-22

申请号：EP07017830.6

申请日：2007-09-12

Applicant: Samsung Display Co., Ltd.

Inventor： Kang, Byeong-Soo

IPC: H05K1/16

CPC classification number: H05K1/16 ,  G02F1/13452 ,  H01Q1/243 ,  H01Q1/38 ,  H05K1/0219 ,  H05K1/0268 ,  H05K1/0298 ,  H05K2201/09145 ,  H05K2201/09809

Abstract: A display device including a display panel and a printed circuit board. The printed circuit board includes an insulating layer, a circuit wire portion, an antenna arranged on the insulating layer and a connection wire portion. The insulating layer includes a base portion and a protruding portion protruded from a side of the base portion. The circuit wire portion is arranged on the base portion. The antenna is arranged on the protruding portion and insulated from the circuit wire portion. The connection wire portion is arranged on the base portion and electrically connected to the antenna. The antenna is exposed outside of the display panel.

公开(公告)号：EP2513969A1

公开(公告)日：2012-10-24

申请号：EP10796242.5

申请日：2010-12-14

Applicant: Qualcomm Incorporated

Inventor： LI, Xia ,  ZHAO, Wei ,  CAO, Yu ,  GU, Shiqun ,  KANG, Seung H. ,  KING, Ming-Chu

IPC: H01L23/552 ,  H01L23/66 ,  H01L23/498 ,  H01L23/48 ,  H01L23/64 ,  H05K1/02

CPC classification number: H01L23/552 ,  H01L23/14 ,  H01L23/49827 ,  H01L23/645 ,  H01L23/66 ,  H01L2223/6616 ,  H01L2223/6622 ,  H01L2223/6638 ,  H01L2924/0002 ,  H01L2924/3011 ,  H05K1/0222 ,  H05K1/0245 ,  H05K3/4602 ,  H05K3/4644 ,  H05K2201/09809 ,  Y10T29/49117 ,  H01L2924/00

Abstract: A system of via structures disposed in a substrate. The system includes a first via structure that comprises an outer conductive layer, an inner insulating layer, and an inner conductive layer disposed in the substrate. The outer conductive layer separates the inner insulating layer and the substrate and the inner insulating layer separates the inner conductive layer and the outer conductive layer. A first signal of a first complementary pair passes through the inner conductive layer and a second signal of the first complementary pair passes through the outer conductive layer. In different embodiments, a method of forming a via structure in an electronic substrate is provided.

Abstract translation: 设置在基板中的通孔结构的系统。 该系统包括第一通孔结构，其包括外部导电层，内部绝缘层和设置在基板中的内部导电层。 外部导电层分离内部绝缘层和基板，内部绝缘层分离内部导电层和外部导电层。 第一互补对的第一信号通过内导电层，第一互补对的第二信号通过外导电层。 在不同的实施例中，提供了一种在电子衬底中形成通孔结构的方法。

公开(公告)号：EP2494598A1

公开(公告)日：2012-09-05

申请号：EP10737421.7

申请日：2010-07-15

Applicant: Xilinx, Inc.

Inventor： WYLAND, Christopher, P.

IPC: H01L23/66

CPC classification number: H01L23/66 ,  H01L23/64 ,  H01L2223/6616 ,  H01L2924/0002 ,  H01L2924/3011 ,  H05K1/0251 ,  H05K1/116 ,  H05K2201/09463 ,  H05K2201/09781 ,  H05K2201/09809 ,  H01L2924/00

Abstract: Vias (106) are typically of a lower impedance than the signal lines (102, 128) connected to them. The noise and reflected signals resulting in impedance mismatch may require circuits to be operated at a frequency far lower than desired. An embodiment avoids impedance mismatch in circuits and achieves an advance in the art by providing a via (106) with higher impedance through the addition of split ring resonators (104, 112, 120, 126) to each end of the via (106).

公开(公告)号：EP2392200A1

公开(公告)日：2011-12-07

申请号：EP10704613.8

申请日：2010-02-01

Applicant: Tyco Electronics Corporation

Inventor： SMEJTEK, Dalibor, J.

IPC: H05K3/36

CPC classification number: H05K3/366 ,  H05K1/117 ,  H05K3/3405 ,  H05K2201/048 ,  H05K2201/09036 ,  H05K2201/09809 ,  H05K2201/10356 ,  H05K2201/10484

Abstract: A printed circuit assembly (10) includes a base printed circuit (12) having a printed circuit receiving area (29) and a plurality of electrical contacts provided on the printed circuit receiving area (30). The printed circuit assembly also includes a secondary printed circuit (14) having a secondary substrate (54) including a mating edge (46) and a plurality of secondary contacts (70) provided along the mating edge. The secondary printed circuit is mounted on the base printed circuit such that the mating edge of the secondary printed circuit is directly engaged with the base printed circuit at the printed circuit receiving area. Each of the secondary contacts is electrically connected to a corresponding one of the electrical contacts of the base printed circuit.

公开(公告)号：EP2208405B1

公开(公告)日：2011-05-18

申请号：EP08845428.5

申请日：2008-11-03

Applicant: Cinterion Wireless Modules GmbH

Inventor： WENDLER, Ralf ,  ROMAHN, Jörg ,  BÖLCKE, Annette

IPC: H05K1/11 ,  H05K1/14

CPC classification number: H05K3/325 ,  H01R12/52 ,  H05K1/0219 ,  H05K1/0243 ,  H05K3/368 ,  H05K2201/0311 ,  H05K2201/09381 ,  H05K2201/09809 ,  H05K2201/10189 ,  H05K2201/10265

Abstract: The invention relates to a configuration, comprising a first circuit board (ELP), which has a contact surface (KF) for contacting a connection element (VE), said contact surface (KF) comprising a central contact point and a concentric ring enclosing said central contact point; a second circuit board (ZLP); and a connection element (VE), which is electrically contacted on a first side with the second circuit board (ZLP) and which comprises a first spring element (FE1) and at least one second spring element (FE2, FE3) on a second side, which is opposite the first side, said first spring element (FE1) being electrically contacted with the central contact point of the first circuit board (ELP) and the at least one second spring element (FE2, FE3) being electrically contacted with the concentric ring of the first circuit board (ELP).

公开(公告)号：EP1981316A3

公开(公告)日：2009-11-04

申请号：EP08251323.5

申请日：2008-04-04

Applicant: Kabushiki Kaisha Toshiba

Inventor： Suzuki, Ryota c/o Toshiba Corporation ,  Tanabe, Masahiro c/o Toshiba Corporation ,  Nakada, Taihei c/o Toshiba Corporation ,  Kumamoto, Tsuyoshi c/o Toshiba Corporation ,  Yamashita, Yuusuke c/o Toshiba Corporation

IPC: H05K1/02

CPC classification number: H05K1/0251 ,  H05K1/0222 ,  H05K1/116 ,  H05K3/429 ,  H05K2201/09454 ,  H05K2201/09618 ,  H05K2201/09718 ,  H05K2201/09809

Abstract: A multilayer high-frequency circuit board includes a signal line layer (102) in which a high-frequency signal line (11) is formed, ground layers (101, 103) which are laminated on both sides of the signal line layer, and an interlayer circuit which is provided in the signal line layer and which includes a ground connecting portion (13) connected to the ground layers and a signal line connecting portion (12) connected to the signal line. The interlayer circuit is characterized in that one of the signal line connecting portion and the ground connecting portion surrounds an outer periphery of the other concentrically with the one being separated from the outer periphery of the other along the signal line layer, and an inner periphery of the one and the outer periphery of the other have a similar shape excluding a complete circle.

公开(公告)号：EP1827061A3

公开(公告)日：2009-09-09

申请号：EP07250735.3

申请日：2007-02-21

Applicant: TEKTRONIX, INC.

Inventor： Ebbutt, Ralph

IPC: H05K1/02 ,  H05K3/34

CPC classification number: H05K1/0219 ,  H01L21/6835 ,  H01L23/49811 ,  H01L23/49816 ,  H01L23/49827 ,  H01L23/49838 ,  H01L23/552 ,  H01L23/66 ,  H01L24/81 ,  H01L2223/6622 ,  H01L2224/11003 ,  H01L2224/16225 ,  H01L2224/81001 ,  H01L2224/81801 ,  H01L2924/01079 ,  H01L2924/09701 ,  H01L2924/14 ,  H01L2924/3011 ,  H01L2924/3025 ,  H05K1/0243 ,  H05K3/3436 ,  H05K2201/09809 ,  H05K2201/10424 ,  H05K2201/10734 ,  H05K2203/0769 ,  H01L2924/00

Abstract: A circuit assembly has two circuit boards parallel to each other and having major faces facing each other. Each major face has a signal contact connected to a signal trace. At least one of the major faces has a ground contact surrounding the signal contact. The signal and ground contacts are connected by way of a column element defining an axis perpendicular to the board faces. The column element has an inner conductor electrically connecting the signal contact, and a shield electrically isolated from and surrounding the inner conductor. A number of the column elements, as well as solder elements, may be supported by a carrier, which is placed between the boards for an electrical connection process, and which then may be dissolved.

公开(公告)号：EP1955410A2

公开(公告)日：2008-08-13

申请号：EP06846450.2

申请日：2006-12-04

Applicant: Cisco Technology, Inc.

Inventor： CHENG, Wheling ,  KARAM, Roger ,  CAMERLO, Sergio

IPC: H01R12/04

CPC classification number: H05K1/0222 ,  H05K1/115 ,  H05K3/429 ,  H05K3/4614 ,  H05K2201/09309 ,  H05K2201/09809 ,  H05K2203/061 ,  Y10T29/49126 ,  Y10T29/49128 ,  Y10T29/49162 ,  Y10T29/49165

Abstract: A method of fabricating a printed circuit board having a coaxial via is disclosed. The method includes assembling a plurality of layers configured in a stack so that the plurality of layers has a top signal layer and a bottom signal layer; forming a hollow via through the plurality of layers to connect GND layers in the printed circuit board, forming or inserting into the hollow via a conductor coated with non-conductive material, covering the top layer and bottom layer with dielectric and patterned signal layers, covering the top layer and bottom layer with a masking agent, plating the top layer and bottom layer with a conductive material that connects signal traces within via, and removing the masking agent from the top layer and bottom layer.

公开(公告)号：EP1863326A1

公开(公告)日：2007-12-05

申请号：EP05727172.8

申请日：2005-03-23

Applicant: Fujitsu Ltd.

Inventor： NAKAMURA, Naoki, c/o FUJITSU LIMITED,

IPC: H05K1/11 ,  H05K1/02 ,  H05K3/46

CPC classification number: H05K1/0251 ,  H05K1/115 ,  H05K3/429 ,  H05K3/4602 ,  H05K2201/09809

Abstract: A signal line (17), a power supply pattern (18) and a ground layer (19) are formed within a board (13). An outer via (27) and an inner via (28) are formed within the board (13). The outer via (27) is connected to the signal line (17). The inner via (28) is connected to the ground layer (24). The outer via serves as a signal line. The inner via serves as a ground. The signal line within a printed wiring board is connected to the outer via without interruption by a ground. The signal lines can spread within the printed wiring board in a complicated pattern as compared with a conventional pattern. Moreover, the impedance matching can reliably be established.

Abstract translation: 在板（13）内形成信号线（17），电源图案（18）和接地层（19）。 外部通孔（27）和内部通孔（28）形成在板（13）内。 外部通路（27）连接到信号线（17）。 内部通孔（28）连接到接地层（24）。 外部通路用作信号线。 内部通道用作地面。 印刷电路板内的信号线与外部通路连接而不被地面中断。 与常规图案相比，信号线可以以复杂的图案在印刷线路板内扩展。 此外，可以可靠地建立阻抗匹配。

公开(公告)号：EP1851833A1

公开(公告)日：2007-11-07

申请号：EP06735673.3

申请日：2006-02-22

Applicant: MOLEX INCORPORATED

Inventor： AVERY, Hazelton, P. ,  CASHER, Patrick, R. ,  NELSON, Richard, A. ,  REGNIER, Kent, E.

IPC: H01R13/658

CPC classification number: H05K1/0219 ,  H01R12/724 ,  H01R13/6464 ,  H01R13/6587 ,  H05K1/0237 ,  H05K1/0245 ,  H05K1/116 ,  H05K3/429 ,  H05K2201/09236 ,  H05K2201/09618 ,  H05K2201/09718 ,  H05K2201/09809 ,  H05K2201/10189

Abstract: Stacked receptacles in a connector that each provide side-by-side differential signal contacts, are attached to a circuit board without additional width to accommodate multiple layers of differential signals by using connector wafer inserts that rotate the side-by-side positioned differential signal contacts to front-to-back contacts.