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    INTERCONNECT BRIDGE CIRCUITRY DESIGNS FOR INTEGRATED CIRCUIT PACKAGE SUBSTRATES
    4.
    发明公开
    INTERCONNECT BRIDGE CIRCUITRY DESIGNS FOR INTEGRATED CIRCUIT PACKAGE SUBSTRATES 审中-公开

    公开(公告)号：EP4439662A1

    公开(公告)日：2024-10-02

    申请号：EP23216585.2

    申请日：2023-12-14

    申请人： Intel Corporation

    发明人： Wang, Lijiang ,  Sharan, Sujit

    IPC分类号： H01L23/538 ,  H01L25/065 ,  H01L23/498

    CPC分类号： H01L23/5385 ,  H01L23/49822 ,  H01L23/49838 ,  H01L25/0655 ,  H01L25/18

    摘要： In one embodiment, an interconnect bridge circuitry includes a first set of bridge-to-die electrical connectors in a first region of the circuitry, a second set of bridge-to-die electrical connectors in a second region of the circuitry, and an interconnection between a bridge-to-die connector of the first set and a bridge-to-die connector of the second set. The interconnection is in a third region of the circuitry between the first region and the second region, and includes a first trace connected to the bridge-to-die electrical connector of the first set, a second trace connected to the bridge-to-die electrical connector of the second set, the second trace parallel with the first trace, and a third trace connected between the first trace and the second trace.

    SEMICONDUCTOR MEMORY DEVICES AND METHOD OF MANUFACTURING THE SAME
    9.
    发明公开
    SEMICONDUCTOR MEMORY DEVICES AND METHOD OF MANUFACTURING THE SAME 审中-实审

    公开(公告)号：EP4429435A2

    公开(公告)日：2024-09-11

    申请号：EP24152566.6

    申请日：2024-01-18

    申请人： Samsung Electronics Co., Ltd.

    发明人： FUTATSUYAMA, Takuya ,  BYEON, Daeseok

    IPC分类号： H10B43/27 ,  H10B43/40 ,  H10B43/50 ,  H01L25/065 ,  H01L25/18

    CPC分类号： H10B43/27 ,  H10B43/40 ,  H10B43/50 ,  H01L25/0657 ,  H01L25/18

    摘要： In some embodiments, a semiconductor memory device includes a peripheral circuit structure, and a first and a second cell array structure. The peripheral circuit structure includes a circuit board, a peripheral circuit on the circuit board, a first insulating layer, and a plurality of first bonding pads on the first insulating layer. The first cell array structure includes a first memory cell array, a first conductive plate structure, a second insulating layer, and pluralities of second and third bonding pads on the second insulating layer. The second cell array structure includes a second memory cell array, a second conductive plate structure, a third insulating layer, and a plurality of fourth bonding pads on the third insulating layer. The first cell array structure and the second cell array structure are sequentially stacked in a vertical direction on the peripheral circuit structure.