公开(公告)号：JP2003282627A

公开(公告)日：2003-10-03

申请号：JP2003070797

申请日：2003-03-14

Applicant: Samsung Electronics Co Ltd ,  三星電子株式会社

Inventor： LEE JIN-HYUK ,  KANG SA YOON ,  KWON DONG-WHEE ,  YOU JI-YONG ,  SHIN HYE-SOO

IPC: H01L21/60 ,  H01L21/76 ,  H01L23/485 ,  H01L23/50 ,  H01L23/52 ,  H01L31/0328

CPC classification number: H01L24/05 ,  H01L24/03 ,  H01L2224/02166 ,  H01L2224/05001 ,  H01L2224/05093 ,  H01L2224/05096 ,  H01L2224/05624 ,  H01L2224/05647 ,  H01L2224/45144 ,  H01L2924/01004 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01074 ,  H01L2924/01079 ,  H01L2924/01327 ,  H01L2924/014 ,  H01L2924/14 ,  H01L2924/00014 ,  H01L2924/00

Abstract: PROBLEM TO BE SOLVED: To provide a semiconductor element having a reinforced bonding pad lower structure, and its fabricating method. SOLUTION: The semiconductor element has an interlayer insulation film formed beneath a bonding pad metal layer while including a contact trench part formed into mesh shape, as a whole, by transferring a pattern 210A, where a plurality of points spaced apart at a constant interval without being coupled each other in the exposure process are arranged in mesh shape as a whole, onto a photoresist film 212 and then passing the pattern 210A through developing and etching processes. Consequently, the yield is enhanced by embodying a meshed contact trench part of fine line width impossible to be formed by current photolithographic process while improving the bonding power and the reliability of the semiconductor element. COPYRIGHT: (C)2004,JPO

Abstract translation: 要解决的问题：提供一种具有加强焊盘下部结构的半导体元件及其制造方法。 解决方案：半导体元件具有在接合焊盘金属层下面形成的层间绝缘膜，同时包括形成为网状的接触沟槽部分，通过传输图案210A，其中多个点以 在曝光过程中不彼此耦合的恒定间隔以网格形状作为整体布置在光致抗蚀剂膜212上，然后通过显影和蚀刻工艺通过图案210A。 因此，通过在提高接合功率和半导体元件的可靠性的同时，通过实现不可能通过电流光刻工艺形成细线宽度的网状接触沟槽部分来提高产量。 版权所有（C）2004，JPO

公开(公告)号：JP2005045268A

公开(公告)日：2005-02-17

申请号：JP2004216538

申请日：2004-07-23

Applicant: Samsung Electronics Co Ltd ,  三星電子株式会社

Inventor： KEN YOKAN ,  KANG SA YOON ,  LEE CHUNG-SUN

IPC: H01L21/44 ,  H01L21/60 ,  H01L23/31 ,  H01L23/485

CPC classification number: H01L24/11 ,  H01L23/3114 ,  H01L24/12 ,  H01L24/16 ,  H01L2224/0231 ,  H01L2224/0401 ,  H01L2224/05124 ,  H01L2224/05144 ,  H01L2224/05147 ,  H01L2224/05155 ,  H01L2224/05164 ,  H01L2224/05166 ,  H01L2224/05171 ,  H01L2224/05644 ,  H01L2224/05647 ,  H01L2224/05655 ,  H01L2224/05664 ,  H01L2224/05666 ,  H01L2224/05671 ,  H01L2224/13099 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01022 ,  H01L2924/01023 ,  H01L2924/01024 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01046 ,  H01L2924/01047 ,  H01L2924/01074 ,  H01L2924/01075 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/07802 ,  H01L2924/00 ,  H01L2924/00014 ,  H01L2924/013

Abstract: PROBLEM TO BE SOLVED: To provide a method for forming a re-wiring bump, a semiconductor chip and mounting structure using the method. SOLUTION: The bump forming method makes the mounting of an LDI chip easy and can enlarge a bump area with the same pad pitch even if an upper portion of a bump 43 is flat in order to minimize the area of a pad 33 in the chip, and the chip and its mounting structure use the method. Thereby, a pad area at the edge of a conventional chip can be minimized, the bump 43 is formed on a flat portion inside the chip, and an electrical connection between the pad 33 and the bump 43 is attained with a re-wiring metal film. COPYRIGHT: (C)2005,JPO&NCIPI

Abstract translation: 要解决的问题：提供一种用于形成再布线凸块的方法，半导体芯片和使用该方法的安装结构。 解决方案：凸块形成方法使得LDI芯片的安装变得容易，并且可以以相同的焊盘间距放大凸起区域，即使凸起43的上部是平坦的，以便使焊盘33的面积最小化 芯片，芯片及其安装结构采用该方法。 因此，可以使传统芯片边缘的焊盘区域最小化，凸块43形成在芯片内的平坦部分上，并且通过重新布线金属膜实现焊盘33和凸块43之间的电连接 。 版权所有（C）2005，JPO＆NCIPI

公开(公告)号：JP2005012207A

公开(公告)日：2005-01-13

申请号：JP2004162791

申请日：2004-06-01

Applicant: Samsung Electronics Co Ltd ,  三星電子株式会社

Inventor： LEE KWAN-JAI ,  KANG SA YOON ,  MOK SEUNG-KON

IPC: H01L27/14 ,  H01L23/00 ,  H01L23/02 ,  H01L23/12 ,  H01L27/146 ,  H04N5/225 ,  H04N5/335

CPC classification number: H04N5/2253 ,  H01L2224/48091 ,  H01L2924/00014

Abstract: PROBLEM TO BE SOLVED: To provide a semiconductor apparatus for imaging a solid object which is thinner than a customary apparatus and is down-sized. SOLUTION: The semiconductor apparatus for imaging a solid object includes: a lens attachment portion; semiconductor chip for imaging the solid object which converts light to a image signal; a conductive substance which is formed in a via-hole formed on a scribe line of the solid semiconductor chip for imaging and electrically connects a bonding pad formed on an upper surface of the solid semiconductor chip for imaging and a terminal formed on its lower surface; and a circuit board which electrically connects them through the terminal formed on the lower surface of the solid semiconductor chip for imaging. Additionally, the semiconductor apparatus for imaging the solid object uses a conductive line formed along the side surface of the semiconductor chip of imaging the solid object instead of the conductive substance. COPYRIGHT: (C)2005,JPO&NCIPI

Abstract translation: 要解决的问题：提供一种用于对比常规装置更薄的固体物体进行成像的半导体装置，并且尺寸较小。 解决方案：用于对固体物体进行成像的半导体装置包括：透镜附接部分; 用于对固体物体进行成像以将光转换成图像信号的半导体芯片; 形成在形成在固体半导体芯片的划线上的通孔中的导电物质，用于成像，并且电连接形成在用于成像的固体半导体芯片的上表面上的焊盘和形成在其下表面上的端子; 以及电路板，其通过形成在固体半导体芯片的下表面上的端子电连接，用于成像。 此外，用于对固体物体进行成像的半导体装置使用沿着半导体芯片的侧表面形成的导电线，而不是导电物质而对固体物体进行成像。 版权所有（C）2005，JPO＆NCIPI

公开(公告)号：JP2005167238A

公开(公告)日：2005-06-23

申请号：JP2004340201

申请日：2004-11-25

Applicant: Samsung Electronics Co Ltd ,  三星電子株式会社

Inventor： PARK SANG HO ,  KANG SA YOON ,  LEE SI-HOON

IPC: H01L21/60 ,  G02F1/13 ,  G02F1/1345 ,  G09F9/00 ,  G09G3/00 ,  H01L21/56 ,  H01L21/58 ,  H01L23/12 ,  H01L23/48 ,  H01L23/498 ,  H05K1/14 ,  H05K3/36

CPC classification number: H01L23/49838 ,  G02F1/13452 ,  H01L21/563 ,  H01L23/4985 ,  H01L2924/0002 ,  H01L2924/12044 ,  H05K1/142 ,  H05K1/147 ,  H05K3/361 ,  H05K2201/09227 ,  H05K2201/10681 ,  H01L2924/00

Abstract: PROBLEM TO BE SOLVED: To provide a more small-sized tape wiring board, and to provide a semiconductor chip package using it.
SOLUTION: Input wiring 222, output wirings 223 and 224 and/or bypass wiring 225 are formed to pass through the inside of portion 226, where the semiconductor chip 241 is mounted on a base film 221. Thereby, the wiring pattern does not pass the outside of the semiconductor chip 241 along the outer contour of the base film 221, the circuit pattern is minimized, and the base film is small-sized.
COPYRIGHT: (C)2005,JPO&NCIPI

Abstract translation: 要解决的问题：提供更小尺寸的胶带线路板，并提供使用它的半导体芯片封装。

解决方案：输入布线222，输出布线223和224和/或旁路布线225形成为穿过半导体芯片241安装在基膜221上的部分226的内部。由此，布线图案 不沿着基膜221的外轮廓通过半导体芯片241的外部，电路图案被最小化，并且基膜是小尺寸的。 版权所有（C）2005，JPO＆NCIPI

公开(公告)号：JP2005057258A

公开(公告)日：2005-03-03

申请号：JP2004212512

申请日：2004-07-21

Applicant: Samsung Electronics Co Ltd ,  三星電子株式会社

Inventor： KANG SA YOON ,  KIM DONG HAN ,  JUNG YE-JUNG

IPC: H01L21/60 ,  G02F1/13 ,  G02F1/1345 ,  H01L23/538 ,  H05K1/11 ,  H05K1/14

CPC classification number: G02F1/13452 ,  H01L23/5387 ,  H01L2224/16 ,  H01L2924/07811 ,  H05K1/118 ,  H05K1/147 ,  H05K2201/068 ,  H05K2201/10681 ,  H01L2924/00

Abstract: PROBLEM TO BE SOLVED: To provide an inexpensive flexible film package module and a method for manufacturing the same. SOLUTION: In the flexible film package and the method for manufacturing the same, a first insulation substrate 10 in which the tape film of the flexible film package module is made of a polyimide material and a second insulation substrate 170 less expensive than the first insulation substrate are used in a linked state. COPYRIGHT: (C)2005,JPO&NCIPI

Abstract translation: 要解决的问题：为了提供廉价的柔性膜包装模块及其制造方法。 解决方案：在柔性膜封装及其制造方法中，第一绝缘基板10，其中柔性膜封装模块的带膜由聚酰亚胺材料制成，第二绝缘基板170比第一绝缘基板 第一绝缘基板以连接状态使用。 版权所有（C）2005，JPO＆NCIPI

公开(公告)号：JP2003243606A

公开(公告)日：2003-08-29

申请号：JP2003028447

申请日：2003-02-05

Applicant: SAMSUNG ELECTRONICS CO LTD

Inventor： SONG YOUNG HEE ,  KANG SA YOON ,  SON MIN YOUNG

IPC: H01L25/18 ,  H01L21/60 ,  H01L23/52 ,  H01L25/065 ,  H01L25/07

Abstract: PROBLEM TO BE SOLVED: To provide an excellent semiconductor chip, facilitated in electric connection as well as heat dissipation, and a laminated chip package, capable of being thinned and multi-functioned. SOLUTION: The semiconductor chip 210 comprises a plurality of bonding pads 211, provided with active surfaces 212, the rear surfaces of the active surfaces 212 or inactive surfaces 213 and side surfaces 215 between the active surfaces 212 and the inactive surfaces 213 while being provided on the active surfaces 212, a plurality of bump pads 216, provided on the inactive surfaces 213 so as to be corresponding to the bonding pads 211, and a plurality of connecting wires 217, provided on the inactive surfaces 213 and extended so as to be exposed in the side surfaces 215. Further, the semiconductor chip 210 comprises at least one set or more of heat dissipating units 219 formed on the inactive surfaces 213. The bump pads 216, the connecting wirings 217 and the heat dissipating units 219 are formed in wiring grooves whereby mutual communication and heat dissipation can be easily realized upon laminating the semiconductor chips. COPYRIGHT: (C)2003,JPO

公开(公告)号：JP2003188207A

公开(公告)日：2003-07-04

申请号：JP2002342552

申请日：2002-11-26

Applicant: SAMSUNG ELECTRONICS CO LTD

Inventor： KWON DONG WHEE ,  KANG SA YOON ,  SONG YUN HEUB ,  LEE JIN HYUK

IPC: H01L23/52 ,  H01L21/3205 ,  H01L21/60 ,  H01L23/485

Abstract: PROBLEM TO BE SOLVED: To provide a semiconductor element, having a bonding pad and its manufacturing method. SOLUTION: The bonding pad has two conductive films and an intermediate layer inbetween them. The intermediate layer has a hybrid form, which is a mixture of a relatively conductive flat board part and a plug/mesh part. The plug/mesh part has a conductive part which is periodically pierced by non- conductive parts or a non-conductive part which is periodically pierced by conductive parts. The width of the conductive part or the non-conductive part in the plug/mesh part is comparatively smaller than that of the flat board part. The hybrid form keeps appropriate balance between the frat board part, where a probe pin contacts and the plug/mesh part which provides an additional path for electric current. COPYRIGHT: (C)2003,JPO