公开(公告)号：US08370691B1

公开(公告)日：2013-02-05

申请号：US13299507

申请日：2011-11-18

Applicant: Chan-Chi Jason Cheng ,  Qin Wei ,  Ting Yew

Inventor： Chan-Chi Jason Cheng ,  Qin Wei ,  Ting Yew

IPC: G01R31/28 ,  G11C29/00 ,  G06F11/00

CPC classification number: G01R31/31816 ,  G06F11/1004 ,  G11C11/41 ,  G11C29/52 ,  G11C2029/0401 ,  H03K19/17764

Abstract: In one embodiment, a programmable logic device (PLD) with configuration memory includes at least one configuration memory cell and soft error detection (SED) logic for checking for errors in data stored by the configuration memory. The SED logic calculates a present data value for the configuration memory for comparison with a pre-calculated data value. A fuse within the PLD is configurable in a first logic state to enable the SED logic to read from the configuration memory cell in calculating the present data value and configurable in a second logic state to prevent the SED logic from reading from the configuration memory cell in calculating the present data value. The SED logic may be tested for correct operation by writing data representing a soft error into the configuration memory cell and enabling the SED logic to read from the configuration memory cell in calculating the present data value.

Abstract translation: 在一个实施例中，具有配置存储器的可编程逻辑器件（PLD）包括至少一个配置存储器单元和用于检查由配置存储器存储的数据中的错误的软错误检测（SED）逻辑。 SED逻辑计算配置存储器的当前数据值，以便与预先计算的数据值进行比较。 PLD内的保险丝可配置成第一逻辑状态，以使得SED逻辑能够在计算当前数据值时从配置存储器单元读取并且可配置在第二逻辑状态以防止SED逻辑从配置存储器单元中读取 计算当前数据值。 可以通过将表示软错误的数据写入配置存储器单元来使SED逻辑被测试以进行正确的操作，并且在计算当前数据值时使SED逻辑能够从配置存储器单元读取。

公开(公告)号：US07902865B1

公开(公告)日：2011-03-08

申请号：US11941031

申请日：2007-11-15

Applicant: Chan-Chi Jason Cheng ,  San-Ta Kow ,  Ann Wu

Inventor： Chan-Chi Jason Cheng ,  San-Ta Kow ,  Ann Wu

IPC: H01L25/00 ,  H03M5/00 ,  G06F17/50

CPC classification number: G06F17/5054 ,  H03M7/30

Abstract: Various techniques are provided to compress and decompress configuration data for use with programmable logic devices (PLDs). In one example, a method includes embedding a first data frame comprising a data set from an uncompressed bitstream into a compressed bitstream. The method also includes embedding a first instruction to instruct a PLD to load the first data frame into a data shift register, embedding a second instruction to instruct the PLD to load a first address associated with the first data frame into an address shift register, and embedding a third instruction to instruct the PLD to load the first data frame from the data shift register into a first row of a configuration memory corresponding to the first address. The method further includes identifying a second data frame comprising the data set in the uncompressed bitstream, and embedding fourth and fifth instructions in place of the second data frame.

Abstract translation: 提供了各种技术来压缩和解压缩与可编程逻辑器件（PLD）一起使用的配置数据。 在一个示例中，一种方法包括将包括来自未压缩比特流的数据集的第一数据帧嵌入到压缩比特流中。 该方法还包括嵌入第一指令以指示PLD将第一数据帧加载到数据移位寄存器中，嵌入第二指令以指示PLD将与第一数据帧相关联的第一地址加载到地址移位寄存器中，以及 嵌入第三指令以指示PLD将第一数据帧从数据移位寄存器加载到与第一地址对应的配置存储器的第一行中。 该方法还包括识别包括未压缩比特流中的数据集的第二数据帧，以及代替第二数据帧嵌入第四和第五指令。

公开(公告)号：US07663401B1

公开(公告)日：2010-02-16

申请号：US11556528

申请日：2006-11-03

Applicant: Chi Minh Nguyen ,  Chan-Chi Jason Cheng ,  Timothy S. Swensen ,  Giai Trinh ,  Yi Chiang

Inventor： Chi Minh Nguyen ,  Chan-Chi Jason Cheng ,  Timothy S. Swensen ,  Giai Trinh ,  Yi Chiang

IPC: H03K19/177

CPC classification number: H03K19/1737

Abstract: A programmable logic device, in accordance with an embodiment of the present invention, includes a plurality of multiplexers, having fuse input terminals and input signal terminals, and a plurality of associated fuses providing fuse signals to the fuse input terminals to control selection of the input signal terminals. The fuses in a first state select a first input signal terminal of the input signal terminals, with a first multiplexer from the plurality of multiplexers receiving a first logic level signal at the first input signal terminal and providing the first logic level signal to the first input signal terminal of a first set of the plurality of multiplexers. The fuses associated with the first set are adapted to be programmed before the fuses associated with the first multiplexer.

Abstract translation: 根据本发明的实施例的可编程逻辑器件包括具有熔丝输入端和输入信号端的多个多路复用器，以及多个相关联的熔丝，为熔丝输入端提供熔丝信号以控制输入的选择 信号端子。 第一状态的熔丝选择输入信号端子的第一输入信号端，来自多个多路复用器的第一多路复用器在第一输入信号端接收第一逻辑电平信号，并将第一逻辑电平信号提供给第一输入端 所述多个多路复用器的第一组的信号端子。 与第一组相关联的保险丝适于在与第一多路复用器相关联的保险丝之前被编程。

公开(公告)号：US07573291B1

公开(公告)日：2009-08-11

申请号：US11934711

申请日：2007-11-02

Applicant: Om Agrawal ,  Manish Garg ,  Chan-Chi Jason Cheng ,  Satwant Singh ,  Ju Shen

Inventor： Om Agrawal ,  Manish Garg ,  Chan-Chi Jason Cheng ,  Satwant Singh ,  Ju Shen

IPC: H03K19/177

CPC classification number: H03K19/17728

Abstract: A programmable logic block within a programmable logic device includes at least two interconnected slices, each of the interconnect slices including at least two interconnected lookup tables. Each interconnected lookup table is adapted to receive input signals from a routing structure and to provide a LUT output signal. At least one of the slices includes a register adapted to register the LUT output signal of a lookup table and at least another of the slices includes fewer such registers than lookup tables.

Abstract translation: 可编程逻辑器件内的可编程逻辑块包括至少两个互连的片，每个互连片包括至少两个互连的查找表。 每个互连的查找表适于从路由结构接收输入信号并提供LUT输出信号。 至少一个切片包括适于注册查找表的LUT输出信号的寄存器，并且至少另一个切片包括比查找表少的这样的寄存器。

公开(公告)号：US20080204073A1

公开(公告)日：2008-08-28

申请号：US11680526

申请日：2007-02-28

Applicant: Satwant Singh ,  Chan-Chi Jason Cheng

Inventor： Satwant Singh ,  Chan-Chi Jason Cheng

IPC: H03K19/173

CPC classification number: H03K19/17752 ,  H03K19/1776 ,  H03K19/17764

Abstract: Systems and methods are disclosed directed to techniques with respect to defective configuration memory cells. For example, in accordance with an embodiment of the present invention, a programmable logic device includes a plurality of configuration memory cells; and at least one spare memory cell, wherein the at least one spare memory cell is adapted to store configuration data to provide to at least one defective configuration memory cell.

Abstract translation: 公开了关于缺陷配置存储器单元的技术的系统和方法。 例如，根据本发明的实施例，可编程逻辑器件包括多个配置存储器单元; 以及至少一个备用存储器单元，其中所述至少一个备用存储器单元适于存储配置数据以提供给至少一个缺陷配置存储器单元。

公开(公告)号：US20070204855A1

公开(公告)日：2007-09-06

申请号：US11745321

申请日：2007-05-07

Applicant: Jason Cheng ,  Kok Tam

Inventor： Jason Cheng ,  Kok Tam

IPC: F24C15/20

CPC classification number: F24C15/2057

Abstract: A device and method for cleaning fans in range or stove hoods by spraying steam onto the fan impeller area on which soot and cooking fumes condense to clean the impeller and wash the accumulated condensates down a drain. By using steam above atmospheric pressure as the cleaning fluid, the device uses significantly less water that other devices that spray water or an aqueous solution to clean the fan blades.

Abstract translation: 通过将蒸汽喷射到风扇叶轮区域上来清洁范围或炉灶罩中的风扇的装置和方法，在该区域上烟灰和烹饪烟雾被冷凝以清洁叶轮并将排出的积聚的冷凝物洗涤。 通过使用高于大气压的蒸汽作为清洗液，该设备使用明显较少的水，其他喷射水或水溶液的设备来清洁风扇叶片。

公开(公告)号：US06861871B1

公开(公告)日：2005-03-01

申请号：US10428885

申请日：2003-05-01

Applicant: Om P. Agrawal ,  Paul R. Bonwick ,  Chan-Chi Jason Cheng

Inventor： Om P. Agrawal ,  Paul R. Bonwick ,  Chan-Chi Jason Cheng

IPC: H03K19/177

CPC classification number: H03K19/17736

Abstract: Cascadable logic block architectures are disclosed for programmable logic devices, such as for high density and high performance complex programmable logic devices. The logic block architectures provide, for example, clusters or groups of logic blocks that may have cascadable inputs and/or product terms to provide flexible logic width and/or depth capability. The logic block architecture may, for example, be implemented in conjunction with a multi-stage interconnect architecture to provide array fuse density and/or interconnect fuse density savings compared to conventional architectures.

Abstract translation: 公开了可编程逻辑器件的级联逻辑块架构，例如用于高密度和高性能复杂可编程逻辑器件。 逻辑块架构提供例如可以具有级联输入和/或产品术语的集群或逻辑块组，以提供灵活的逻辑宽度和/或深度能力。 例如，与常规架构相比，逻辑块架构可以结合多级互连架构来实现，以提供阵列熔丝密度和/或互连熔丝密度。

公开(公告)号：US06828823B1

公开(公告)日：2004-12-07

申请号：US10439602

申请日：2003-05-16

Applicant: Cyrus Tsui ,  Benny Ma ,  Om P. Agrawal ,  Ju Shen ,  Sam Tsai ,  Jack Wong ,  Chan-Chi Jason Cheng

Inventor： Cyrus Tsui ,  Benny Ma ,  Om P. Agrawal ,  Ju Shen ,  Sam Tsai ,  Jack Wong ,  Chan-Chi Jason Cheng

IPC: H03K19177

CPC classification number: H03K19/17752 ,  H03K19/1776 ,  H03K19/17768

Abstract: An integrated circuit includes non-volatile and volatile memory, with the volatile memory controlling the integrated circuit's functionality. Various techniques are disclosed for programming the different types of memory through one or more data ports to provide in-system programmability and dynamic reconfigurability. External configuration devices are not required if the data from the non-volatile memory is transferred directly to the volatile memory.

Abstract translation: 集成电路包括非易失性和易失性存储器，易失性存储器控制集成电路的功能。 公开了用于通过一个或多个数据端口对不同类型的存储器进行编程以提供系统内可编程性和动态可重构性的各种技术。 如果来自非易失性存储器的数据直接传输到易失性存储器，则不需要外部配置设备。

公开(公告)号：US20180219509A1

公开(公告)日：2018-08-02

申请号：US15422355

申请日：2017-02-01

Applicant: Robert Martinson ,  Cormac Wicklow ,  Jason Cheng ,  Arthur Cheung ,  Heinrich von Bunau ,  Darin S. Birtwhistle ,  Hyung Paek ,  Robert McClymond

Inventor： Robert Martinson ,  Cormac Wicklow ,  Jason Cheng ,  Arthur Cheung ,  Heinrich von Bunau ,  Darin S. Birtwhistle ,  Hyung Paek ,  Robert McClymond

IPC: H02S30/20 ,  H02S40/32 ,  H02S40/36 ,  H02S40/34 ,  H02S20/23

CPC classification number: H02S30/20 ,  H02S20/23 ,  H02S30/10 ,  H02S40/32 ,  H02S40/34 ,  H02S40/36 ,  Y02B10/12 ,  Y02B10/14

Abstract: Disclosed are apparatuses and methods for an apparatus that has a flexible mounting substrate, one or more flexible photovoltaic modules attached to the flexible mounting substrate, one or more inverters attached to the flexible mounting substrate and electrically connected to the one or more flexible photovoltaic modules, a flexible electrical conduit electrically connected to the one or more inverters and to the one or more flexible photovoltaic modules, a plurality of mounting features, and a plurality of flexible connectors that extend between the flexible mounting substrate and one corresponding mounting feature, that is configured to be positioned above a structure and secured to the structure without penetrating roofing of the structure.

公开(公告)号：US20080289171A1

公开(公告)日：2008-11-27

申请号：US11751765

申请日：2007-05-22

Applicant: Jason Cheng

Inventor： Jason Cheng

IPC: H01M6/00

CPC classification number: H01M2/266 ,  H01M2/0207 ,  H01M2/22 ,  H01M2/30 ,  H01M10/0436 ,  H01M10/049 ,  H01M2002/0205 ,  Y10T29/49108

Abstract: The present invention relates to an improved method for assembling a stacked plate electrochemical device. According to an exemplary embodiment of the invention, two pairs of electrodes are provided: two cathodes and two anodes. Each electrode in each pair is connected to the other electrode via conductive interconnects. The pairs of electrodes are then folded together forming an electrode package, such that the cathodes and anodes alternate position within the electrode package. A number of electrode packages are then stacked together depending on the desired number of electrodes in the stacked plate cell. The stacked electrodes are then placed in a cell can and the conductive interconnects are connected to the cell can terminals to form the stacked plate electrochemical device. Processes according to exemplary embodiments of the present invention result in a faster, more efficient assembly time for the stacked plate electrochemical device.

Abstract translation: 本发明涉及一种组装叠层板电化学装置的改进方法。 根据本发明的示例性实施例，提供两对电极：两个阴极和两个阳极。 每对中的每个电极通过导电互连连接到另一个电极。 然后将电极对折叠在一起形成电极封装，使得阴极和阳极在电极封装内交替位置。 然后根据堆叠板电池中所需的电极数，将多个电极封装件堆叠在一起。 然后将堆叠的电极放置在电池罐中，并且导电互连件连接到电池罐端子以形成堆叠板电化学装置。 根据本发明的示例性实施例的方法导致堆叠板式电化学装置的更快，更有效的组装时间。