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公开(公告)号：US20080211062A1
公开(公告)日：2008-09-04
申请号：US11681235
申请日：2007-03-02
IPC分类号： H01L29/20 , H01L21/20 , H01L21/283
摘要： A semiconductor device and a manufacturing method thereof are provided which enable reduction and enhanced stability of contact resistance between the back surface of a nitride substrate and an electrode formed thereover. A nitride semiconductor device includes an n-type GaN substrate (1) over which a semiconductor element is formed, and an n-electrode (10) as a metal electrode formed over the back surface of the GaN substrate (1). A connection layer (20) is formed between the GaN substrate (1) and the n-electrode (10), and the connection layer (20) is composed of a material that is other than nitride semiconductors and that contains silicon.
摘要翻译： 提供一种半导体器件及其制造方法，其能够降低并增强氮化物衬底的背表面和形成在其上的电极之间的接触电阻的稳定性。 氮化物半导体器件包括在其上形成半导体元件的n型GaN衬底（1）和形成在GaN衬底（1）的背面上的作为金属电极的n电极（10）。 在GaN衬底（1）和n电极（10）之间形成连接层（20），并且连接层（20）由除氮化物半导体之外并且包含硅的材料构成。
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2.发明授权Method of manufacturing semiconductor device including steps of forming both insulating film and epitaxial semiconductor on substrate 失效制造半导体器件的方法包括在衬底上形成绝缘膜和外延半导体的步骤公开(公告)号：US06737315B2
公开(公告)日：2004-05-18
申请号：US10212249
申请日：2002-08-06
IPC分类号： H01L218242
CPC分类号： H01L21/762 , H01L21/823481 , H01L23/544 , H01L2223/54453 , H01L2924/0002 , H01L2924/00
摘要： A substrate surface (10S) is thermally oxidized to form an oxide film. The oxide film is patterned so that the substrate surface (10S) in an active region is exposed. An oxide film (20) is thereby provided. An exposed substrate surface (10S) is thermally oxidized, to form a thermal oxide film. This thermal oxide film is thereafter removed at least in an element forming region. A silicon film (41) is epitaxially grown on the exposed substrate surface (10S). Thereafter the silicon film (41) is polished by CMP to an extent that an upper surface of the silicon film after polishing is not more than an upper surface of the oxide film (20) in height. Next, the surface of the silicon film is thermally oxidized to form a thermal oxide film. After ion implantation of various types, this thermal oxide film is removed.
摘要翻译： 将基板表面（10S）热氧化以形成氧化膜。 图案化氧化膜，使得有源区域中的衬底表面（10S）暴露。 由此提供氧化膜（20）。 暴露的衬底表面（10S）被热氧化，以形成热氧化膜。 此后，至少在元件形成区域中除去该热氧化膜。 在暴露的基板表面（10S）上外延生长硅膜（41）。 此后，通过CMP对硅膜（41）进行抛光，使抛光后的硅膜的上表面的高度不超过氧化膜（20）的上表面。 接着，将硅膜的表面热氧化，形成热氧化膜。 在各种类型的离子注入之后，去除该热氧化膜。
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公开(公告)号：US06707099B2
公开(公告)日：2004-03-16
申请号：US10218444
申请日：2002-08-15
IPC分类号： H01L29792
CPC分类号： H01L29/66651 , H01L21/28123 , H01L29/1033
摘要： A semiconductor device less susceptible to inverse narrow channel effect and its manufacturing method are provided. A silicon nitride film (13) is adopted as element isolation regions; the silicon nitride film (13) has a smaller etch rate than a sacrificial silicon oxide film (7) which serves as a sacrificial layer during ion implantation (8). This prevents formation of recesses in the silicon nitride film (13) during the removal of the sacrificial silicon oxide film (7), which weakens the strength of the electric fields at the gate edges. Weakening the strength of the electric fields at the gate edges suppresses the inverse narrow channel effect, so that the MOS transistor offers a characteristic closer to a characteristic in which the threshold voltage keeps a constant value independently of the channel width. Thus an MOS transistor having a good characteristic can be manufactured.
摘要翻译： 提供了一种不易反向窄通道效应的半导体器件及其制造方法。 采用氮化硅膜（13）作为元件隔离区域; 氮化硅膜（13）具有比在离子注入期间用作牺牲层的牺牲氧化硅膜（7）更小的蚀刻速率（8）。 这样可以防止在去除牺牲氧化硅膜（7）期间在氮化硅膜（13）中形成凹陷，这削弱了栅极边缘处的电场强度。 削弱栅极边缘处的电场强度抑制了反向窄通道效应，使得MOS晶体管具有更接近阈值电压独立于沟道宽度保持恒定值的特性。 因此，可以制造具有良好特性的MOS晶体管。
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公开(公告)号：US06518635B1
公开(公告)日：2003-02-11
申请号：US09610862
申请日：2000-07-06
申请人： Katsuomi Shiozawa , Toshiyuki Oishi , Yuji Abe , Yasunori Tokuda
发明人： Katsuomi Shiozawa , Toshiyuki Oishi , Yuji Abe , Yasunori Tokuda
IPC分类号： H01L27108
CPC分类号： H01L29/517 , H01L21/26506 , H01L21/26586 , H01L21/28167
摘要： A major object of the present invention is to provide an improved semiconductor device so as to be able to reduce gate electric field concentration at a channel edge, suppress decrease in the threshold during MOSFET operation and reduce the leakage current. A gate insulation film is formed on a semiconductor substrate. A gate electrode is formed on the semiconductor substrate with the gate insulation film therebetween. The dielectric constant of the gate insulation film is not uniform in the surface.
摘要翻译： 本发明的主要目的是提供一种改进的半导体器件，以便能够降低沟道边缘处的栅极电场集中，抑制MOSFET操作期间阈值的降低并减少漏电流。 在半导体衬底上形成栅极绝缘膜。 栅电极形成在半导体衬底上，其间具有栅极绝缘膜。 栅极绝缘膜的介电常数在表面上不均匀。
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公开(公告)号：US06387743B1
公开(公告)日：2002-05-14
申请号：US09978540
申请日：2001-10-18
申请人： Katsuomi Shiozawa , Syuichi Ueno , Yasuyoshi Itoh
发明人： Katsuomi Shiozawa , Syuichi Ueno , Yasuyoshi Itoh
IPC分类号： H01L218238
CPC分类号： H01L21/82385 , H01L21/823842 , H01L21/823864
摘要： A semiconductor device and manufacturing method capable of forming shallow extension regions in insulated-gate transistors. A side wall material containing about 1 to 20% of phosphorus, such as PSG, is deposited on the sides of an opening to a film thickness of tens of nanometers to about 100 nm and etched back to form phosphorus-containing side walls respectively adjacent to boron-containing side walls. An interlayer insulating film of silicon nitride etc. is then formed on the silicon nitride film. A thermal process performed during formation of the interlayer insulating film forms N-type extension regions in the NMOS region through a diffusion where phosphorus contained in the phosphorus-containing side walls serves as the diffusion source and P-type extension region in the PMOS region through a diffusion where boron contained in the boron-containing side walls serves as the diffusion source.
摘要翻译： 一种能够在绝缘栅晶体管中形成浅扩展区的半导体器件和制造方法。 含有约1〜20％磷的侧壁材料（如PSG）沉积在开口的两侧至几十纳米至约100nm的膜厚度并被回蚀以形成分别毗邻的含磷侧壁 含硼侧壁。 然后在氮化硅膜上形成氮化硅等的层间绝缘膜。 在形成层间绝缘膜期间进行的热处理通过扩散形成NMOS区域中的N型延伸区域，其中含磷侧壁中的磷用作扩散源，PMOS区域中的P型延伸区域通过 包含在含硼侧壁中的硼用作扩散源的扩散。
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公开(公告)号：US06333540B1
公开(公告)日：2001-12-25
申请号：US09668472
申请日：2000-09-25
申请人： Katsuomi Shiozawa , Syuichi Ueno , Yasuyoshi Itoh
发明人： Katsuomi Shiozawa , Syuichi Ueno , Yasuyoshi Itoh
IPC分类号： H01L2701
CPC分类号： H01L21/82385 , H01L21/823842 , H01L21/823864
摘要： A semiconductor device and manufacturing method capable of forming shallow extension regions in insulated-gate transistors. A side wall material containing about 1 to 20% of phosphorus, such as PSG, is deposited on the sides of an opening to a film thickness of tens of nanometers to about 100 nm and etched back to form phosphorus-containing side walls respectively adjacent to boron-containing side walls. An interlayer insulating film of silicon nitride etc. is then formed on the silicon nitride film. A thermal process performed during formation of the interlayer insulating film forms N-type extension regions in the NMOS region through a diffusion where phosphorus contained in the phosphorus-containing side walls serves as the diffusion source and P-type extension region in the PMOS region through a diffusion where boron contained in the boron-containing side walls serves as the diffusion source.
摘要翻译： 一种能够在绝缘栅晶体管中形成浅扩展区的半导体器件和制造方法。 含有约1〜20％磷的侧壁材料（如PSG）沉积在开口的两侧至几十纳米至约100nm的膜厚度并被回蚀以形成分别毗邻的含磷侧壁 含硼侧壁。 然后在氮化硅膜上形成氮化硅等的层间绝缘膜。 在形成层间绝缘膜期间进行的热处理通过扩散形成NMOS区域中的N型延伸区域，其中含磷侧壁中的磷用作扩散源，PMOS区域中的P型延伸区域通过 包含在含硼侧壁中的硼用作扩散源的扩散。
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公开(公告)号：US07842962B2
公开(公告)日：2010-11-30
申请号：US11274422
申请日：2005-11-16
IPC分类号： H01L33/00
CPC分类号： H01L21/28575 , H01L33/32 , H01L33/40
摘要： A P-type electrode material is provided on a top surface of a P-type contact layer. The P-type electrode material is formed with an AuGa film, an Au film, a Pt film, and an Au film. The AuGa film is provided on the P-type contact layer. The Au film is provided on the AuGa film. The Pt film is provided on the Au film. The Au film is provided on the Pt film. With this, a nitride semiconductor device having a P-type electrode which can decrease a contact resistance between a P-type contact layer and the P-type electrode is obtained.
摘要翻译： P型电极材料设置在P型接触层的顶表面上。 P型电极材料由AuGa膜，Au膜，Pt膜和Au膜形成。 AuGa膜设置在P型接触层上。 Au膜设置在AuGa膜上。 Pt膜设置在Au膜上。 Au膜设置在Pt膜上。 由此，可以获得具有能够降低P型接触层与P型电极之间的接触电阻的P型电极的氮化物半导体器件。
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公开(公告)号：US20090146308A1
公开(公告)日：2009-06-11
申请号：US12327874
申请日：2008-12-04
申请人： Katsuomi Shiozawa , Kyozo Kanamoto , Hiroshi Kurokawa , Yasunori Tokuda , Kyosuke Kuramoto , Hitoshi Sakuma
发明人： Katsuomi Shiozawa , Kyozo Kanamoto , Hiroshi Kurokawa , Yasunori Tokuda , Kyosuke Kuramoto , Hitoshi Sakuma
CPC分类号： H01L33/40 , H01L33/32 , H01L2924/0002 , H01S5/0425 , H01S5/22 , H01S5/2214 , H01S5/32341 , H01L2924/00
摘要： A nitride semiconductor device with a p electrode having no resistance between itself and other electrodes, and a method of manufacturing the same are provided. A p electrode is formed of a first Pd film, a Ta film, and a second Pd film, and on a p-type contact layer of a nitride semiconductor. On the second Pd film, a pad electrode is formed. The second Pd film is formed on the entire upper surface of the Ta film which forms part of the p electrode, and serves as an antioxidant film that prevents oxidation of the Ta film. Preventing oxidation of the Ta film, the second Pd film can reduce the resistance that may exist between the p electrode and the pad electrode, thereby preventing a failure in contact between the p electrode and the pad electrode and providing the p electrode with low resistance.
摘要翻译： 提供一种具有在其自身与其他电极之间不具有电阻的p电极的氮化物半导体器件及其制造方法。 p电极由第一Pd膜，Ta膜和第二Pd膜形成，并且在氮化物半导体的p型接触层上形成。 在第二Pd膜上形成焊盘电极。 第二Pd膜形成在形成p电极的一部分的Ta膜的整个上表面上，并且用作防止Ta膜氧化的抗氧化膜。 为了防止Ta膜的氧化，第二Pd膜可以降低p电极和焊盘电极之间可能存在的电阻，从而防止p电极和焊盘电极之间的接触不良，并提供具有低电阻的p电极。
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公开(公告)号：US20090127661A1
公开(公告)日：2009-05-21
申请号：US12271946
申请日：2008-11-17
申请人： Katsuomi Shiozawa , Kyozo Kanamoto , Toshiyuki Oishi , Hiroshi Kurokawa , Kazushige Kawasaki , Shinji Abe , Hitoshi Sakuma
发明人： Katsuomi Shiozawa , Kyozo Kanamoto , Toshiyuki Oishi , Hiroshi Kurokawa , Kazushige Kawasaki , Shinji Abe , Hitoshi Sakuma
CPC分类号： H01S5/32341 , H01S5/0425 , H01S5/22 , H01S2301/173
摘要： Semiconductor devices, in particular nitride semiconductor devices for use in the manufacture of laser diodes, prevent peeling-off of the electrode, and at the same time reduces the complexity of processes and a reduction in yield. A nitride semiconductor device according to the invention includes a P-type nitride semiconductor layer with a ridge on its surface, an SiO2 film covering at least the side face of the ridge, an adherence layer formed on a surface of the SiO2 film and composed mainly of silicon, and a P-type electrode formed on the upper surface of the ridge and on a surface of the adherence layer.
摘要翻译： 半导体器件，特别是用于制造激光二极管的氮化物半导体器件，防止电极剥离，并且同时降低了工艺的复杂性和产量的降低。 根据本发明的氮化物半导体器件包括其表面上具有脊的P型氮化物半导体层，至少覆盖脊的侧面的SiO 2膜，形成在SiO 2膜的表面上并且主要组成的粘附层 的硅，以及形成在脊的上表面上和粘附层的表面上的P型电极。
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公开(公告)号：US20080311694A1
公开(公告)日：2008-12-18
申请号：US11946917
申请日：2007-11-29
IPC分类号： H01L33/00
CPC分类号： H01S5/22 , B82Y20/00 , H01S5/0425 , H01S5/2009 , H01S5/2086 , H01S5/2214 , H01S5/34333
摘要： An SiO2 film is formed on a semiconductor layer stack, the SiO2 film having a thickness da and an etch rate Ra in buffered (BHF). A waveguide ridge with the SiO2 film thereon is formed using a resist pattern 76. An SiN film is formed on top and both sides of the waveguide ridge, while leaving the resist pattern in place, the SiN film having a thickness db and an etch rate Rb in BHF, where 1
摘要翻译： 在半导体层堆叠上形成SiO 2膜，SiO 2膜具有厚度da和缓冲（BHF）中的蚀刻速率Ra。 使用抗蚀剂图案76形成其上具有SiO 2膜的波导脊。SiN膜在波导脊的顶部和两侧形成，同时使抗蚀剂图案保持在适当位置，SiN膜具有厚度db和蚀刻速率 Rb在BHF中，其中1 <（db / Rb）/（da / Ra）。 然后通过剥离去除SiN膜的抗蚀剂图案和上覆部分，以在SiN膜中形成开口。 用BHF湿法蚀刻预定的时间段，从而将SiN膜从波导脊除去，同时使SiN膜保持在适当的位置。
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